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1/3 january 2002 psd3xx zpsd3xx zpsd3xxv psd3xxr zpsd3xxr zpsd3xxrv low cost field programmable microcontroller peripherals features summary single supply voltage: C 5 v10% for psd3xx, zpsd3xx, psd3xxr, zpsd3xxr C 2.7 to 5.5 v for zpsd3xxv, zpsd3xxrv up to 1 mbit of eprom up to 16 kbit sram input latches programmable i/o ports page logic programmable security figure 1. packages pldcc44 (j) cldcc44 (l) pqfp44 (m) tqfp44 (u) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i psd3xx family psd3xx zpsd3xx zpsd3xxv psd3xxr zpsd3xxr zpsd3xxrv low cost microcontroller peripherals table of contents 1 introduction .................................................................................................................. .........................................1 2 notation ...................................................................................................................... ..........................................2 3 key features .................................................................................................................. ......................................4 4 psd3xx family feature summary ................................................................................................. .....................5 5 partial listing of microcontrollers supported ................................................................................. .......................6 6 applications .................................................................................................................. ........................................6 7 zpsd background ............................................................................................................... .................................6 7.1 integrated power management tm operation .............................................................................................7 8 operating modes (mcu configurations) .......................................................................................... ..................10 9 programmable address decoder (pad)............................................................................................ .................12 10 i/o port functions ........................................................................................................... ....................................15 10.1 csioport registers.......................................................................................................... ....................15 10.2 port a (pa0-pa7)........................................................................................................... ..........................16 10.2.1 port a (pa0-pa7) in multiplexed address/data mode................................................................16 10.2.2 port a (pa0-pa7) in non-multiplexed address/data mode ........................................................17 10.3 port b (pb0-pb7)........................................................................................................... ..........................18 10.3.1 port b (pa0-pa7) in multiplexed address/data mode................................................................18 10.3.2 port b (pa0-pa7) in non-multiplexed address/data mode ........................................................19 10.4 port c (pc0-pc2) ........................................................................................................... .........................20 10.5 ale/as input pin ........................................................................................................... ..........................20 11 psd memory ................................................................................................................... ...................................21 11.1 eprom...................................................................................................................... ..............................21 11.2 sram (optional)............................................................................................................ ..........................21 11.3 page register (optional) ................................................................................................... ......................21 11.4 programming and erasure.................................................................................................... ...................21 12 control signals .............................................................................................................. .....................................22 12.1 ale or as ................................................................................................................... .............................22 12.2 wr or r/w.................................................................................................................. .............................22 12.3 rd/e/ds (ds option not available on 3x1 devices) ........................................................................... .....22 12.4 psen or psen ............................................................................................................... .........................22 12.5 a19/csi .................................................................................................................... ...............................23 12.6 reset input ................................................................................................................ ..............................24 13 program/data space and the 8031 .............................................................................................. ......................26 14 systems applications......................................................................................................... .................................27 15 security mode ................................................................................................................ .....................................30 16 power management............................................................................................................. ...............................30 16.1 csi input.................................................................................................................. ................................30 16.2 cmiser bit ................................................................................................................. ...............................30 16.3 turbo bit (zpsd only)...................................................................................................... .......................31 16.4 number of product terms in the pad logic................................................................................... .........31 16.5 composite frequency of the input signals to the pad logic..................................................................3 2 16.6 loading on i/o pins ........................................................................................................ .........................33 17 calculating power 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ii psd3xx family psd3xx zpsd3xx zpsd3xxv psd3xxr zpsd3xxr zpsd3xxrv low cost microcontroller peripherals table of contents (cont.) 18 specifications............................................................................................................... .......................................37 18.1 absolute maximum ratings ................................................................................................... ..................37 18.2 operating range ............................................................................................................ .........................37 18.3 recommended operating conditions........................................................................................... ...........37 18.4 pin capacitance............................................................................................................ ...........................37 18.5 ac/dc characteristics ?psd3xx/zpsd3xx (all 5 v devices) ..............................................................38 18.6 ac/dc characteristics ?psd3xxv (3 v devices only)......................................................................... ..39 18.7 timing parameters ?psd3xx/zpsd3xx (all 5 v devices)....................................................................40 18.8 timing parameters ?zpsd3xxv (3 v devices only) ............................................................................ ..42 18.9 timing diagrams for psd3xx parts........................................................................................... ............44 18.10 ac testing ................................................................................................................ ...............................65 19 pin assignments .............................................................................................................. ...................................66 20 package information .......................................................................................................... .................................67 21 package drawings ............................................................................................................. .................................68 22 psd3xx product ordering information .......................................................................................... ....................72 22.1 psd3xx selector guide...................................................................................................... ....................72 22.2 part number construction ................................................................................................... ....................73 22.3 ordering information....................................................................................................... .........................73 23 data sheet revision history .................................................................................................. .............................80 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
1 1.0 introduction programmable peripheral psd3xx family field-programmable microcontroller peripheral the low cost psd3xx family integrates high-performance and user-configurable blocks of eprom, programmable logic, and optional sram into one part. the psd3xx products also provide a powerful microcontroller interface that eliminates the need for external ?lue logic? the parts integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller. the major functional blocks of the psd3xx include: two programmable logic arrays 256kb to 1 mb of eprom optional 16 kb sram input latches programmable i/o ports page logic programmable security. the psd3xx family architecture (figure 1) can efficiently interface with, and enhance, almost any 8- or 16-bit microcontroller system. this solution provides microcontrollers the following: chip-select logic, control logic, and latched address signals that are otherwise implemented discretely port expansion (reconstructs lost microcontroller i/o) expanded microcontroller address space (up to 16 times) an eprom (with security) and optional sram compatible with 8031-type architectures that use separate program and data space interface to shared external resources. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 2 2. notation for a complete product comparison, refer to table 1. psd3xx references the standard version of the psd3xx family, which are ideal for general-purpose embedded control applications. psd3xxr sram-less version of the psd3xx. if you don? require the 16 kb sram or need a larger external sram, go with this part to save cost. zpsd3xx has improved technology that helps reduce current consumption using the turbo bit. excellent if you require a 5 v version of the psd3xx that uses less power. zpsd3xxr sram-less version of the zpsd3xx. zpsd3xxv 2.7 v to 5.5 v operation, ideal for very low-power and low-voltage applications. zpsd3xxrv sram-less version of the zpsd3xxv. throughout this data sheet, references are made to the psd3xx. in most cases, these references also cover the entire family. exceptions will be noted. references, such as ?x1 only?cover all parts that have a 301 or 311 in the part number. use the following table to determine what references cover which product versions: reference psd3xx psd3xxr zpsd3xx zpsd3xxr zpsd3xxv zpsd3xxrv psd3xx xx x x x x psd psd3xx only x x non-zpsd x x zpsd only zpsd3xx x x x x non-v versions x x x x v versions only v suffix x x zpsd3xxv only sram-less xx x non-r the psd3xx i/o ports can be used for: standard i/o ports programmable chip select outputs address inputs demultiplexed address outputs a data bus port for non-multiplexed mcu applications a data bus ?epeater?port that shares and arbitrates the local mcu data bus with external devices. implementing your design has never been easier than with psdsoft st s software development suite. using psdsoft, you can do the following: configure your psd3xx to work with virtually any microcontroller specify what you want implemented in the programmable logic using a high-level hardware description language (hdl) simulate your design download your design to the part using a programmer. 1.0 introduction (cont.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 3 prog. port exp. port c pc0 pc2 es0 es1 es2 es3 es4 es5 es6 es7 prog. control signals a19/csi reset wr/r/w rd/e / ds ale/as bhe/psen pad a reset wr ale/as rd pad b a11?15 prog. port exp. port b pb0 pb7 prog. port exp. port a pa0 pa7 a19/csi reset ale/as a19/csi a8?10 wr rd ale/as l a t c h l a t c h ad8?d15 ad0?d7 d8?15 13 p.t. 27 p.t. optional page logic * logic in eprom 256kb to 1mb a16?18 cs8 cs10 cs0 cs7 optional sram 16k bit ** d0?7 rs0 a0?7 ad0?d7/d0?7 d8?15 csioport prog. chip configuration x8, x16 mux or non?ux busses security mode 16/8 mux csioport track mode selects p3?0 figure 1. psd3xx family architecture * * not available for 3x1 devices. ** sram not available on ??versions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 4 3.0 key features o single-chip programmable peripheral for microcontroller-based applications o 256k to 1 mbit of uv eprom with the following features: configurable as 32, 64, or 128 k x 8; or as 16, 32, or 64 k x 16 divided into eight equally-sized mappable blocks for optimized address mapping as fast as 70 ns access time, which includes address decoding o optional 16 kbit sram is configurable as 2k x 8 or 1k x 16. the access time can be as quick as 70 ns, including address decoding. o 19 i/o pins that can be individually configured for : microcontroller i/o port expansion programmable address decoder (pad) i/o latched address output open-drain or cmos output o two programmable arrays (pad a and pad b) replace your pld or decoder, and have the following features: up to 18 inputs and 24 outputs 40 product terms (13 for pad a and 27 for pad b) ability to decode up to 1 mb of address without paging o microcontroller logic that eliminates the need for external ?lue logic?has the following features: ability to interface to multiplexed and non-multiplexed buses built-in address latches for multiplexed address/data bus ale and reset polarity are programmable (reset polarity not programmable on v-versions) multiple configurations are possible for interface to many different microcontrollers o optional built-in page logic expands the mcu address space by up to 16 times o programmable power management with standby current as low as 1? for low-voltage version cmiser bit programmable option to reduce ac power consumption in memory turbo bit (zpsd only)programmable bit to reduce ac and dc power consumption in the pads. o track mode that allows other microcontrollers or host processors to share access to the local data bus o built-in security locks the device and pad decoding configuration o wide operating voltage range v-versions: 2.7 to 5.5 volts others: 4.5 to 5.5 volts o available in a variety of packaging (44-pin pldcc, cldcc, tqfp, and pqfp) o simple, menu-driven software (psdsoft) allows configuration and design entry on a pc. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 5 use the following table to determine which psd product will fit your needs. refer back to this page whenever there is confusion as to which part has what features. 4.0 psd3xx family feature summary typical # pld eprom sram page turbo bus standby part inputs size size reg voltage bit width current psd301r 14 256 kb 5 v x8 or x16 50 ? psd311r 14 256 kb 5 v x8 50 ? psd302r 18 512 kb x 5 v x8 or x16 50 ? psd312r 18 512 kb x 5 v x8 50 ? psd303r 18 1 mb x 5 v x8 or x16 50 ? psd313r 18 1 mb x 5 v x8 50 ? zpsd301r 14 256 kb 5 v x x8 or x16 10 ? zpsd311r 14 256 kb 5 v x x8 10 ? zpsd302r 18 512 kb x 5 v x x8 or x16 10 ? zpsd312r 18 512 kb x 5 v x x8 10 ? zpsd303r 18 1 mb x 5 v x x8 or x16 10 ? zpsd313r 18 1 mb x 5 v x x8 10 ? psd301 14 256 kb 16 kb 5 v x8 or x16 50 ? psd311 14 256 kb 16 kb 5 v x8 50 ? psd302 18 512 kb 16 kb x 5 v x8 or x16 50 ? psd312 18 512 kb 16 kb x 5 v x8 50 ? psd303 18 1 mb 16 kb x 5 v x8 or x16 50 ? psd313 18 1 mb 16 kb x 5 v x8 50 ? zpsd301 14 256 kb 16 kb 5 v x x8 or x16 10 ? zpsd311 14 256 kb 16 kb 5 v x x8 10 ? zpsd302 18 512 kb 16 kb x 5 v x x8 or x16 10 ? zpsd312 18 512 kb 16 kb x 5 v x x8 10 ? zpsd303 18 1 mb 16 kb x 5 v x x8 or x16 10 ? zpsd313 18 1 mb 16 kb x 5 v x x8 10 ? zpsd301v 1 14 256 kb 16 kb 2.7 v x x8 or x16 1 ? zpsd311v 1 14 256 kb 16 kb 2.7 v x x8 1 ? zpsd302v 1 18 512 kb 16 kb x 2.7 v x x8 or x16 1 ? zpsd312v 1 18 512 kb 16 kb x 2.7 v x x8 1 ? zpsd303v 1 18 1 mb 16 kb x 2.7 v x x8 or x16 1 ? zpsd313v 1 18 1 mb 16 kb x 2.7 v x x8 1 ? notes: 1. low power versions of the zpsd3xx (zpsd3xxv) can only accept an active-low level reset input. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
5.0 partial listing of microcontrollers supported psd3xx family 6 o motorola family: 68hc11, 68hc16, m68000/10/20, m68008, m683xx, 68hc05c0 o intel family : 80c31, 80c51, 80c196/198, 80c186/188 o philips family: 80c31 and 80c51 based mcus o zilog: z8, z80, z180 o national: hpc16000, hpc46400 o echelon/motorola/toshiba: neuron 3150 chip 6.0 applications o telecommunications: cellular phone digital pbx digital speech fax digital signal processing (dsp) o portable industrial equipment: industrial control measurement meters data recorders o instrumentation o medical instrumentation: hearing aids monitoring equipment diagnostic tools o computersnotebooks, portable pcs, and palm-top computers: peripheral control (fixed disks, laser printers, etc.) modem interface mcu peripheral interface portable and battery-powered systems have recently become major embedded control application segments. as a result, the demand for electronic components having extremely low power consumption has increased dramatically. recognizing this trend, st developed a new lower power 3xx part, denoted zpsd3xx. the z stands for zero-power because zpsd products virtually eliminate the dc component of power consumption, reducing it to standby levels. virtual elimination of the dc component is the basis for the words ?ero-power?in the zpsd name. zpsd products also minimize the ac power component when the chip is changing states. the result is a programmable microcontroller peripheral family that replaces discrete circuit components, while drawing less power. 7.0 zpsd background obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 7 7.0 zpsd background (cont.) integrated power management tm operation upon each address or logic input change to the zpsd, the device powers up from low power standby for a short time. then the zpsd consumes only the necessary power to deliver new logic or memory data to its outputs as a response to the input change. after the new outputs are stable, the zpsd latches them and automatically reverts back to standby mode. the i cc current flowing during standby mode and during dc operation is identical and is only a few microamperes. the zpsd automatically reduces its dc current drain to these low levels and does not require controlling by the csi (chip select input). disabling the csi pin unconditionally forces the zpsd to standby mode independent of other input transitions. the only significant power consumption in the zpsd occurs during ac operation. the zpsd contains the first architecture to apply zero power techniques to memory and logic blocks. figure 2 compares zpsd zero power operation to the operation of a discrete solution. a standard microcontroller (mcu) bus cycle usually starts with an ale (or as) pulse and the generation of an address. the zpsd detects the address transition and powers up for a short time. the zpsd then latches the outputs of the pad, eprom and sram to the new values. after finishing these operations, the zpsd shuts off its internal power, entering standby mode. the time taken for the entire cycle is less than the zpsds ?ccess time. the zpsd will stay in standby mode while its inputs are not changing between bus cycles. in an alternate system implementation using discrete eprom, sram, and other discrete components, the system will consume operating power during the entire bus cycle. this is because the chip select inputs on the memory devices are usually active throughout the entire cycle. the ac power consumption of the zpsd may be calculated using the composite frequency of the mcu address and control signals, as well as any other logic inputs to the zpsd. ale discrete eprom, sram & logic address eprom access sram access eprom access i cc zpsd zpsd zpsd time figure 2. zpsd power operation vs. discrete implementation obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 8 name type description when the data bus is 8 bits: this pin is for 8031 or compatible mcus that use psen to separate program space from data space. in this case, psen is bhe/ used for reads from the eprom. note: if your mcu does not psen i output a psen signal, pull up this pin to v cc . when the data bus is 16 bits: this pin is bhe. when low, d8-d15 are read from or written to. note: in programming mode, this pin is pulsed between v pp and 0 v. the following control signals can be connected to this port, based on wr/v pp your mcu (and the way you configure the psd in psdsoft): or i 1. wractive-low write pulse. r/w/v pp 2. r/wactive-high read/active-low write input. note: in programming mode, this pin must be tied to v pp . the following control signals can be connected to this port, based on rd/e/ds i your mcu (and the way you configure the psd in psdsoft): 1. rdactive-low read input. 2. ee clock input. 3. ds?ctive-low data strobe input (3x2/3x3 devices only) the following control signals can be connected to this port: 1. csi?ctive-low chip select input. if your mcu supports a chip select output, and you want the psd to save power when not a19/csi i selected, use this pin as a chip select input. 2. if you don? wish to use the csi feature, you may use this pin as an additional input (logic or address) to the pad. a19 can be latched (with ale/as), or a transparent logic input. psd3xx/zpsd3xx: this pin is user-programmable and can be configured to reset on a high- or low-level input. reset must be applied for at least 100 ns. reset i zpsd3xxv: this pin is not configurable, and the chip will only reset on an active-low level input. reset must be applied for at least 500 ns, and no operations may take place for an additional 500 ns minimum. (see figure 8.) if you use an mcu that has a multiplexed bus: connect ale or as to this pin. the polarity of this pin is configurable. the trailing edge of ale/as latches all multiplexed address inputs ale/as i (and bhe where applicable). if you use an mcu that does not have a multiplexed bus: if your mcu uses ale/as, connect the signal to this pin. otherwise, use this pin for a generic logic input to the pad. (non-3x1 devices only.) these pins make up port a. these port pins are configurable, and pa0 can have the following functions: (see figure 5a and 5b) pa1 1. track ad7-ad0. this feature repeats the mcu address and data pa2 i/o bus on all port a pins. pa3 2. mcu i/oin this mode, the direction of the pin is defined by its pa4 direction bit, which resides in the direction register. pa5 3. latched address output. pa6 4. cmos or open-drain output. pa7 5. if your mcu is non-multiplexed: data bus input?onnect your data bus (d0-7) to these pins. see figure 3. legend: the type column abbreviations are: i = input only; i/o = input/output; p = power. table 2. psd3xx pin descriptions obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 9 table 2. psd3xx pin descriptions (cont.) name type description these pins make up port b. these port pins are configurable, and pb0 can have the following functions: (see figure 6) pb1 1. mcu i/o in this mode, the direction of the pin is defined by its pb2 direction bit, which resides in the direction register. pb3 2. chip select output each of pb0-3 has four product terms pb4 i/o available per pin, while pb4-7 have 2 product terms each. pb5 see figure 4. pb6 3. cmos or open-drain. pb7 4. if your mcu is non-multiplexed, and the data bus width is 16 bits: data bus input?onnect your data bus (d8-d15) to these pins. see figure 3. these pins make up port c. these port pins are configurable, and can have the following functions (see figure 7): 1. pad input?hen configured as an input, a bit individually pc0 becomes an address or a logic input, depending on your psdsoft pc1 i/o design file. when declared as an address, the bit(s) can be latched pc2 with ale/as. 2. pad output?hen configured as an output (i.e. there is an equation written for it in your psdsoft design file), there is one product term available to it. ad0/a0 if your mcu is multiplexed: ad1/a1 these pins are the multiplexed, low-order address/data byte ad2/a2 (ad0-ad7). as inputs, address information is latched by the ale/as ad3/a3 i/o signal and used internally by the psd. the pins also serve as mcu ad4/a4 data bus inputs or outputs, depending on the mcu control signals ad5/a5 (rd, wr, etc.). ad6/a6 if your mcu is non-multiplexed: ad7/a7 these pins are the low-order address inputs (a0-a7) ad8/a8 if your mcu is multiplexed with a 16-bit data bus: ad9/a9 these pins are the multiplexed, high-order address/data byte ad10/a10 (ad8-ad15). as inputs, address information is latched by the ad11/a11 i/o ale/as signal and used internally the psd. the pins also ad12/a12 serve as mcu data bus inputs or outputs, depending on the mcu ad13/a13 control signals (rd, wr, etc.). ad14/a14 if your mcu is non-multiplexed or has a 8-bit data bus: ad15/a15 these pins are the high-order address inputs (a8-a15). gnd p ground pin v cc p supply voltage input. legend: the type column abbreviations are: i = input only; i/o = input/output; p = power. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 10 8.0 operating modes (mcu configurations) the psd3xxs four operating modes enable it to interface directly to most 8- and 16-bit microcontrollers with multiplexed and non-multiplexed address/data busses. the 16-bit modes are not available to some devices; see table 1. the following are the four operating modes available: o multiplexed 8-bit address/data bus o multiplexed 16-bit address/data bus o non-multiplexed 8-bit data bus o non-multiplexed 16-bit data bus please read the section below that corresponds to your type of mcu. then check the appropriate figure (3a/3b/3c/3d) to determine your pin connections. table 3 lists the port connections in tabular form. multiplexed 8-bit address/data bus (figure 3a) this mode is used to interface to microcontrollers with a multiplexed 8-bit data bus. since the low-order address and data are multiplexed together, your mcu will output an ale or as signal. the psd3xx contains a transparent latch to demultiplex the address/data lines internally. all you have to do is connect the ale/as signal and select 8-bit multiplexed bus mode in psdsoft. if your mcu outputs more than 16 bits of address, and you wish to connect them to the psd, connect a16-a18 to port c and a19 to a19/csi, where applicable. multiplexed 16-bit address/data bus (figure 3b) this mode is used to interface to microcontrollers with a multiplexed 16-bit data bus. since the low address bytes and data are multiplexed together, your mcu will output an ale or as signal. the psd3xx contains a transparent latch to demultiplex the address/data lines internally. all you have to do is connect the ale/as signal and select 8-bit multiplexed bus mode in psdsoft. if your mcu outputs more than 16 bits of address, and you wish to connect them to the psd, connect a16-a18 to port c and a19 to a19/csi, where applicable. non-multiplexed 8-bit data bus (figure 3c) this mode is used to interface to microcontrollers with a non-multiplexed 8-bit data bus. connect the mcus address bus to ad0/a0-ad15/a15 on the psd. connect the data bus signals of your mcu to port a of the psd. if your mcu outputs more than 16 bits of address, and you wish to connect them to the psd, connect a16-a18 to port c and a19 to a19/csi, where applicable. non-multiplexed 16-bit data bus (figure 3d) this mode is used to interface to microcontrollers with a non-multiplexed 16-bit data bus. connect the mcus address bus to ad0/a0-ad15/a15 on the psd. connect the low byte data bus signals of your mcu to port a, and the high byte data output of your mcu to port b of the psd. if your mcu outputs more than 16 bits of address, and you wish to connect them to the psd, connect a16-a18 to port c and a19 to a19/csi, where applicable. for users with multiplexed mcus that have data multiplexed on address lines other than a0-a7 note: you can still use the psd3xx, but you will have to connect your data to port a (and port b where required), as shown in figure 3c or 3d. that is, you will be connecting it as if you were using a non-multiplexed mcu. in this case, you must connect the ale/as signal so that the address will still be properly latched. this option is not available on the 3x1 versions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 11 figure 3a. connecting a psd3xx to an 8-bit multiplexed-bus mcu your 8-bit mcu psd3xx pa pb pc ad0 -ad7 a8 -a15 ale/as psen r/ w or wr rd/e / ds 1 a19 / csi reset a16-a18 2 figure 3b. connecting a psd3xx to a 16-bit multiplexed-bus mcu your 16-bit mcu psd3xx pa pb pc ad0 -ad7 ad8 -ad15 ale/as bhe/ psen r/ w or wr rd/e / ds 1 a19 / csi reset a16-a18 2 figure 3c. connecting a psd3xx to an 8-bit non-multiplexed-bus mcu your 8-bit mcu psd3xx pa pb pc d0 -d7 a0-a15 ale/as psen r/ w or wr rd/e / ds 1 a19 / csi reset a16-a18 2 figure 3d. connecting a psd3xx to a 16-bit non-multiplexed-bus mcu your 16-bit mcu psd3xx pa pb pc d0 -d15 a0-a15 ale/as bhe / psen r/ w or wr rd/e / ds 1 a19 / csi reset a16-a18 2 d0 -d7 d8-d15 notes: 1. ds is a valid input on 3x2/3x3 and devices only. 2. connect a16-a18 to port c if your mcu outputs more than 16 bits of address. 8.0 operating modes (mcu configurations) (cont.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 12 multiplexed address/ data non-multiplexed address/ data 8-bit data bus i/o or low-order address port a lines or low-order multiplexed d0?7 data bus byte address/data byte port b i/o and/or cs0?s7 i/o and/or cs0?s7 ad0/a0?d7/a7 low-order multiplexed address/data byte low-order address bus byte ad8/a8?d15/a15 high-order address high-order address bus byte bus byte 16-bit data bus i/o or low-order address port a lines or low-order multiplexed low-order data bus byte address/data byte port b i/o and/or cs0?s7 high-order data bus byte ad0/a0?d7/a7 low-order multiplexed address/data byte low-order address bus byte ad8/a8?d15/a15 high-order multiplexed address/data byte high-order address bus byte 8.0 operating modes (mcu configurations) (cont.) table 3. bus and port configuration options 9.0 programmable address decoder (pad) the psd3xx contains two programmable arrays, referred to as pad a and pad b (figure 4). pad a is used to generate chip select signals derived from the input address to the internal eprom blocks, sram, i/o ports, and track mode signals. pad b outputs to ports b and c for off-chip usage. pad b can also be used to extend the decoding to select external devices or as a random logic replacement. pad a and pad b receive the same inputs. the pad logic is configured by psdsoft based on the designers input. the pads non-volatile configuration is stored in a re-programmable cmos eprom. windowed packages are available for erasure by the user. see table 4 for a list of pad a and pad b functions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
notes: 1. csi is a power-down signal. when high, the pad is in stand-by mode and all its outputs become non-active. see tables 12 and 13. 2. reset deselects all pad output signals. see tables 10 and 11. 3. a18, a17, and a16 are internally multiplexed with cs10, cs9, and cs8, respectively. either a18 or cs10, a17 or cs9, and a16 or cs8 can be routed to the external pins of port c. port c pins can be configured as either input or output, individually. 4. p 0 ? 3 are not included on 3x1 devices. 5. ds is not available on 3x1 devices. figure 4. pad description ale or as wr or r/w a19 a18 a17 a16 a15 a14 a13 a12 a11 es0 es1 es2 es3 es4 es5 es6 es7 rs0 csioport csadin csadout1 csadout2 cs0/pb0 cs1/pb1 cs2/pb2 cs3/pb3 cs4/pb4 cs5/pb5 cs6/pb6 cs7/pb7 cs8/pc0 cs9/pc1 cs10/pc2 rd/e/ds 8 eprom block select lines csi reset sram block select * track mode control signals p 0 p 1 p 2 p 3 i/o base address pad b pad a psd3xx family 13 * sram no available on ??versions obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 14 function pad a and pad b inputs a19/csi when the psd is configured to use csi and while csi is a logic 1, the pad deselects all of its outputs and enters a power-down mode (see tables 12 and 13). when the psd is configured to use a19, this signal is another input to the pad. a16?18 these are general purpose inputs from port c. see figure 4, note 3. a11?15 these are address inputs. p0?3 these are inputs from the page register (not available on 3x1 versions). rd/e/ds this is the read pulse or strobe input. (ds not available on 3x1 versions). wr or r/w this is the write pulse or r/w select signal. ale/as this is the ale or as input to the chip. use to demultiplex address and data. reset this deselects all outputs from the pad; it can not be used in product term equations. see tables 10 and 11. pad a outputs these are internal chip-selects to the 8 eprom banks. each bank can es0?s7 be located on any boundary that is a function of one product term of the pad address inputs. rs0 this is an internal chip-select to the sram. its base address location is a function of one term of the pad address inputs. this internal chip-select selects the i/o ports. it can be placed on any csioport boundary that is a function of one product term of the pad inputs. see tables 5a and 5b. this internal chip-select, when port a is configured as a low-order address/data bus in the track mode controls the input direction of port a. csadin is gated externally to the pad by the internal read signal. when csadin csadin and a read operation are active, data presented on port a flows out of ad0/a0?d7/a7 . this chip-select can be placed on any boundary that is a function of one product term of the pad inputs. see figure 5b. this internal chip-select, when port a is configured as a low-order address/data bus in track mode, controls the output direction of port a. csadout1 is gated externally to the pad by the ale signal. when csadout1 csadout1 and the ale signal are active, the address presented on ad0/a0?d7/a7 flows out of port a . this chip-select can be placed on any boundary that is a function of one product term of the pad inputs. see figure 5b. this internal chip-select, when port a is configured as a low-order address/data bus in the track mode, controls the output direction of port a. csadout2 must include the write-cycle control signals as part of its csadout2 product term. when csadout2 is active, the data presented on ad0/a0?d7/a7 flows out of port a . this chip-select can be placed on any boundary that is a function of one product term of the pad inputs. see figure 5b. pad b outputs cs0?s3 these chip-select outputs can be routed through port b. each of them is a function of up to four product terms of the pad inputs. cs4?s7 these chip-select outputs can be routed through port b. each of them is a function of up to two product terms of the pad inputs. cs8?s10 these chip-select outputs can be routed through port c. see figure 4, note 3. each of them is a function of one product term of the pad inputs. table 4. psd3xx pad a and pad b functions obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
15 psd3xx family 10.0 i/o port functions the psd3xx has three i/o ports (ports a, b, and c) that are configurable at the bit level. this permits great flexibility and a high degree of customization for specific applications. the next section describes the control registers for the ports. following that are sections that describe each port. figures 5 through 7 show the structure of ports a through c, respectively. note: any unused input should be connected directly to ground or pulled up to v cc (using a 10k to 100k resistor). 10.1 csioport registers control of the ports is primarily handled through the csioport registers. there are 24 bytes in the address space, starting at the base address labeled csioport. since the psd3xx uses internal address lines a15-a8 for decoding, the csioport space will occupy 2 kbytes of memory, on a 2 kbyte boundary. this resolution can be improved to reduce wasted address space by connecting lower order address lines (a7 and below) to port c. using this method, resolution down to 256 kbytes may be achieved. the csioport space must be defined in your psdsoft design file . the following tables list the registers located in the csioport space. 16-bit users note when referring to table 5b, realize that ports a and b are still accessible on a byte basis. note: when accessing port b on a 16-bit data bus, bhe must be low. table 5a. csioport registers for 8-bit data busses note: 1. zpsd only. offset (in hex) type of from csioport access register name base address allowed port a pin register +2 read port a direction register +4 read/write port a data register +6 read/write port b pin register +3 read port b direction register +5 read/write port b data register +7 read/write power management register (note 1) +10 read/write page register +18 read/write table 5b. csioport registers for 16-bit data busses note: 1. zpsd only. offset (in hex) type of from csioport access register name base address allowed port a/b pin register +2 read port a/b direction register +4 read/write port a/b data register +6 read/write power management register (note 1) +10 read/write page register +18 read/write obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 16 psd3xx family 10.0 i/o port functions ( cont.) 10.2 port a (pa0-pa7) the control registers of port a are located in csioport space; see table 5. 10.2.1 port a (pa0-pa7) in multiplexed address/data mode each pin of port a can be individually configured. the following table summarizes what the control registers (in csioport space) for port a do: note: 1. default value is the value after reset. default value register name 0 value 1 value (note 1) port a pin register sampled logic level sampled logic level x at pin = ? at pin = ? port a direction register pin is configured pin is configured 0 as input as output port a data register data in dff = ? data in dff = ? 0 mcu i/o mode the default configuration of port a is mcu i/o. in this mode, every pin can be set (at run- time) as an input or output by writing to the respective pins direction flip-flop (dir ff, figure 5a). as an output, the pin level can be controlled by writing to the respective pins data flip-flop (dff, figure 5a). the pin register can be read to determine logic level of the pin. the contents of the pin register indicate the true state of the psd driving the pin through the dff or an external source driving the pin. pins can be configured as cmos or open-drain using st s psdsoft software. open-drain pins require external pull-up resistors. latched address output mode alternatively, any bit(s) of port a can be configured to output low-order demultiplexed address bus bit. the address is provided by the internal psd address latch, which latches the address on the trailing edge of ale/as. port a then outputs the desired demultiplexed address bits. this feature can eliminate the need for an external latch (for example: 74ls373) if you have devices that require low-order latched address bits. although any pin of port a may output an address signal, the pin is position-dependent. in other words, pin pa0 of port a may only pass a0, pa1 only a1, and so on. track mode track mode sets the entire port to track the signals on ad0/a0-ad7/a7, depending on specific address ranges defined by the pads csadin, csadout1, and csadout2 signals. this feature lets the user interface the microcontroller to shared external resources without requiring external buffers and decoders. in track mode, port a effectively operates as a bi-directional buffer, allowing external mcus or host processors to access the local data bus. keep the following information in mind when setting up track mode: o the direction is controlled by: ale/as rd/e or rd/e/ds (ds on non-3x1 devices only) wr or r/w pad outputs csadout1, csadout2, and csadin defined in psdsoft design. o when csadout1 and ale/as are true, the address on ad0/a0-ad7/a7 is output on port a. note: carefully check the generation of csadout1 to ensure that it is stable during the ale/as pulse. o when csadout2 is active and a write operation is performed, the data on the ad0/a0-ad7/a7 input pins flows out through port a. o when csadin is active and a read operation is performed, the data on port a flows out through the ad0/a0-ad7/a7 pins. o port a is tri-stated when none of the above conditions exist. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
note: 1. the expression for csadout2 must include the following write operation cycle signals: for crrwr = 0, csadout2 must include wr = 0. for crrwr = 1, csadout2 must include e = 1 and r/w = 0. psd3xx family 17 internal read csadin internal ale pa0 pa7 a11 a15 a16 a19 ad8 ad15 csadout1 csadout2 (1) ale or as ad0 ?d7 rd/e wr or r / w control decoder latch pad i o note: 1. cmos/od determines whether the output is open drain or cmos. read pin port a pin enable latched addr out mcu i/o out adn/ dn read data write data ale read dir write dir reset ck d r g d r d ck r cmos / od (1) i n t e r n a l a d d r / d a t a b u s a d 0 / a d 7 dff latch dir ff control mux 10.2.2 port a (pa0-pa7) in non-multiplexed address/data mode in this mode, port a becomes the low-order data bus byte of the chip. when reading an internal location, data is presented on port a pins to the mcu. when writing to an internal location, data present on port a pins from the mcu is written to the desired location. 10.0 i/o port functions ( cont.) figure 5a. port a pin structure figure 5b. port a track mode obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 18 psd3xx family 10. i/o port functions ( cont.) 10.3 port b (pb0-pb7) the control registers of port b are located in csioport space; see table 5a and 5b. 10.3.1 port b (pb0-pb7) in multiplexed address/data mode each pin of port b can be individually configured. the following table summarizes what the control registers (in csioport space) for port b do: note: 1. default value is the value after reset. default value register name 0 value 1 value (note 1) port b pin register sampled logic level sampled logic level x at pin = ? at pin = ? port b direction register pin is configured pin is configured 0 as input as output port b data register data in dff = ? data in dff = ? 0 mcu i/o mode the default configuration of port b is mcu i/o. in this mode, every pin can be set (at run-time) as an input or output by writing to the respective pins direction flip-flop (dir ff, figure 6). as an output, the pin level can be controlled by writing to the respective pins data flip-flop (dff, figure 6). the pin register can be read to determine logic level of the pin. the contents of the pin register indicate the true state of the psd driving the pin through the dff or an external source driving the pin. pins can be configured as cmos or open-drain using st s psdsoft software. open-drain pins require external pull-up resistors. chip select output alternatively, each bit of port b can be configured to provide a chip-select output signal from pad b. pb0-pb7 can provide cs0-cs7, respectively. the functionality of these pins is not limited to chip selects only; they can be used for generic combinatorial logic as well. each of the cs0-cs3 signals is comprised of four product terms, and each of the cs4-cs7 signals is comprised of two product terms. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 19 psd3xx family read pin read data port b pin cmos/od (1) mcu i/o out write data ck d r dff enable mux dn csn control dir ff d ck r write dir reset read dir i n t e r n a l i n t e r n a l c s o u t d a t a b u s b u s c s 0 7 d 8 d 1 5 note: 1. cmos/od determines whether the output is open drain or cmos. figure 6. port b pin structure 10.3.2 port b (pb0-pb7) in 16-bit multiplexed address/data mode in this mode, port b becomes the low-order data bus byte to the mcu chip. when reading an internal high-order location, data is presented on port b pins to the mcu. when writing to an internal high-order location, data present on port b pins from the mcu is written to the desired location. 10. i/o port functions ( cont.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 20 cs8 / cs9 / c s10 from pad to pad a16/a17/a18 latched address input qd en logic input d e m u x address in or chip select out input or output set by psdsoft 2 psdsoft 2 port c i/o 1 (pc0 / p c1/ p c2) ale notes: 1. port c pins can be individually configured as inputs or outputs, but not both. pins can be individually configured as address or logic and latched or transparent, except for the 3x1 devices, which must be set to all address or all logic. 2. psdsoft sets this configuration prior to run-time based on your psdsoft design file. figure 7. port c (pc0-pc2) pin structure 10.4 port c (pc0-pc2) each pin of port c (figure 7) can be configured as an input to pad a and pad b, or as an output from pad b. as inputs, the pins are referenced as a16-a18. although the pins are given this reference, they can be used for any address or logic input. [for example, a8-a10 could be connected to those pins to improve the resolution (boundaries) of cs0-cs7 to 256 bytes.] how they are defined in the psdsoft design file determines: whether they are address or logic inputs whether the input is transparent or latched by the trailing edge of ale/as. notes: 1) if the inputs are addresses, they are routed to pad a and pad b, and can be used in any or all pad equations. 2) a logic input is routed to pad b and can be used for boolean equations that are implemented in any or all of the cs0-cs10 pad b outputs. alternately, pc0-pc2 can become cs8-cs10 outputs, respectively, providing the user with more external chip-select pad outputs. each of the signals (cs8-cs10) is comprised of one product term. 10. i/o port functions ( cont.) 10.5 ale/as input pin the ale/as pin may be used as a generic logic input signal to the pads if a non-multiplexed mcu configuration is chosen in psdsoft. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 21 11. psd memory the following sections explain the various memory blocks and memory options within the psd3xx. 11.1 eprom for all of the psd3xx devices, the eprom is built using zero-power technology. this means that the eprom powers up only when the address changes. it consumes power for the necessary time to latch data on its outputs. after this, it powers down and remains in standby mode until the next address change. this happens automatically, and the designer has to do nothing special. the eprom is divided into eight equal-sized banks. each bank can be placed in any address location by programming the pad. bank0-bank7 are selected by pad a outputs es0-es7, respectively. there is one product term for each bank select (esi). refer to table 1 to see the size of the eprom for each psd device. 11.2 sram (optional) like the eprom, the optional sram in the psd3xx devices is built using zero-power technology. all psd3xx parts which do not have an r suffix contain 2 kbytes of sram (table 1). the sram is selected by the rs0 output of the pad. there is one product term dedicated to rs0. if your design requires a sram larger than 2k x 8, then use one of the ramless (r versions) of the 3xx devices with an external sram. the external sram can be addressed trhough port a and all require logic will be taken care of by the psd3xxr. 11.3 page register (optional) all psd3xx parts, except 3x1devices, have a four-bit page register. thus the effective address space of your mcu can be enlarged by a factor of 16. each bit of the page register can be individually read or written. the page register is located in csioport space (at offset 18h); see table 5. the page register is connected to the lowest nibble of the data bus (d3-d0). the outputs of the page register, p3-p0, are connected to pad a, and therefor can be used in any chip select (internal or external) equations. the contents of the page register are reset to zero at power-up and after any chip-level reset. 11.4 programming and erasure programming the device can be done using the following methods: st s main programmerpsdprowhich is accessible through a parallel port. ? st s programmer used specifically with the psd3xxpep300. st s discontinued programmermagic pro. ? a 3rd party programmer, such as data i/o. information for programming the device is available directly from st . please contact your local sales representative. also, check our web site ( www.st .com /psm ) for information related to 3rd party programmers. upon delivery from st or after each erasure (using windowed part), the psd3xx device has all bits in pad and eprom in the hi state (logic 1). the configuration bits are in the lo state (logic 0). to clear all locations of their programmed contents (assuming you have a windowed version), expose the windowed device to an ultra-violet (uv) light source. a dosage of 30 w second/cm 2 is required for psd3xx devices, and 40 w second/cm 2 for low-voltage (v suffix) devices. this dosage can be obtained with exposure to a wavelength of 2537 ? and intensity of 12000 ?/cm 2 for 40 to 45 minutes for the psd3xx and 55 to 60 minutes for the low-voltage (v suffix) devices. the device should be approximately 1 inch (2.54 cm) from the source, and all filters should be removed from the uv light source prior to erasure. the psd3xx devices will erase with light sources having wavelengths shorter than 4000 ?. however, the erasure times will be much longer than when using the recommended 2537 ? wavelength. note: exposure to sunlight will eventually erase the device. if used in such an environment, the package window should be covered with an opaque substance. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 22 12.0 control signals consult your mcu data sheet to determine which control signals your mcu generates, and how they operate. this section is intended to show which control signals should be connected to what pins on the psd3xx. you will then use psdsoft to configure the psd3xx, based on the combination of control signals that your mcu outputs, for example rd, wr, and psen. the psd3xx is compatible with the following control signals: ale or as (polarity is programmable) wr or r/w rd/e or rd/e/ds (ds for non-3x1 devices only) bhe or psen a19/csi reset (polarity is programmable except on low voltage versions with the v suffix). 12.1 ale or as connect the ale or as signal from your mcu to this pin where applicable, and program the polarity using psdsoft. the trailing edge (when the signal goes inactive) of ale or as latches the address on any pins that have an address input. if you are using a non-multiplexed-bus mcu that does not output an ale or as signal, this pin can be used for a generic input to the pad. note: if your data is multiplexed with address lines other than a0-a7 , connect your address pins to ad0/a0-ad15/a15, and connect your data to port a (and port b where applicable), and connect the ale/as signal to this pin. 12.2 wr or r/w your mcu should output a stand-alone write signal (wr) or a multiplexed read/write signal (r/w). in either case, the signal should be connected to this pin. 12.3 rd/e/ds (ds option not available on 3x1 devices) your mcu should output any one of rd, e (clock), or ds. in any case, connect the appropriate signal to this pin. 12.4 bhe or psen o if your mcu does not output either of these signals, tie this pin to vcc (through a series resistor), and skip to the next signal. o if you use an 8-bit 8031 compatible mcu that outputs a separate signal when accessing program space, such as psen, connect it to this pin. you would then use psdsoft to configure the eprom in the psd3xx to respond to psen only or psen and rd. if you have an 8031 compatible mcu, refer to the ?rogram/data space and the 8031?section for further information. o if you are using a 16-bit mcu, connect the bhe (or similar signal) output to this pin. bhe enables accessing of the upper byte of the data bus. see table 6 for information on how this signal is used in conjunction with the a0 address line. bhe a 0 operation 0 0 whole word 0 1 upper byte from/to odd address 1 0 lower byte from/to even address 1 1 none table 6. truth table for bhe and address bit a0 (16-bit mcus only) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 23 12.0 control signals (cont.) 12.5 a19/csi this pin is configured using psdsoft to be either a chip select for the entire psd device or an additional pad input. if your mcu can generate a chip-select signal, and you wish to save power, use the psd chip select feature. otherwise, use this pin as an address or logic input. o when configured as csi (active-low psd chip select): a low on this pin keeps the psd in normal operation. however, when a high is detected on the pin, the psd enters power-down mode. see tables 7a and 7b for information on signal states during power-down mode. see section 16 for details about the reduction of power consumption. o when configured as a19, the pin can be used as an additional input to the pads. it can be used for address or logic. it can also be ale/as dependent or a transparent input, which is determined by your psdsoft design file. in a19 mode, the psd is always enabled. port configuration mode(s) state ad0?0/ad15/a15 all input (hi-z) mcu i/o unchanged port pins pa0?a7 tracking ad0/a0-ad7/a7 input (hi-z) latched address out logic 1 mcu i/o unchanged port pins pb0?b7 chip select outputs, cs0?s7, cmos logic 1 chip select outputs, cs0?s7, open drain hi-z port pins pc0?c2 address or logic inputs, a16-a18 input (hi-z) chip select outputs, cs8?s10, cmos only logic 1 table 7a. signal states during power-down mode internal signal state component internal signal during power-down pad a and pad b cs0?s10 logic 1 (inactive) csadin, csadout1, csadout2, csioport, logic 0 (inactive) es0-es7, rs0 all registers in csioport n/a address space, including: 3 direction 3 data all unchanged 3 page 3 pmr (turbo bit, zpsd only) table 7b. internal states during power-down note: n/a = not applicable obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 24 12.0 control signals (cont.) 12.6 reset input this is an asynchronous input to initialize the psd device. refer to tables 8a and 8b for information on device status during and after reset. the standard-voltage psd3xx and zpsd3xx (non-v) devices require a reset input that is asserted for at least 100 nsec. the psd will be functional immediately after reset is de-asserted. for these standard-voltage devices, the polarity of the reset input signal is programmable using psdsoft (active-high or active-low), to match the functionality of your mcu reset. note: it is not recommended to drive the reset input of the mcu and the reset input of the psd with a simple rc circuit between power on ground. the input threshold of the mcu and the psd devices may differ, causing the devices to enter and exit reset at different times because of slow ramping of the signal. this may result in the psd not being operational when accessed by the mcu. it is recommended to drive both devices actively. a supervisory device or a gate with hysteresis is recommended. for low-voltage zpsd3xxv devices only, the reset input must be asserted for at least 500 nsec. the zpsd3xxv will not be functional for an additional 500 nsec after reset is de-asserted (see figure 8). these low voltage zpsd3xxv devices must use an active-low polarity signal for reset. unlike the standard psds, the reset polarity for the zpsd3xxv is not programmable. if your mcu operates with an active high reset, you must invert this signal before driving the zpsd3xxv reset input. you must design your system to ensure that the psd comes out of reset and the psd is active before the mcu makes its first access to psd memory. depending on the characteristics and speed of your mcu, a delay between the psd reset and the mcu reset may be needed. signal state just signal state after reset port configured mode of operation during reset (note 1) ad0/a0- all input (hi-z) mcu address ad15/a15 and/or data mcu i/o input (hi-z) input (hi-z) tracking input (hi-z) active track port pins ad0/a0-ad7/a7 mode pa0-pa7 psd3xx, logic 0 mcu address latched address out zpsd3xx zpsd3xxv hi-z mcu address mcu i/o input (hi-z input (hi-z) chip select outputs, psd3xx, logic 1 per cs equations port pins cs0-cs7, cmos zpsd3xx pb0-pb7 zpsd3xxv hi-z per cs equations chip select outputs, psd3xx, hi-z per cs equations cs0-cs7, open drain zpsd3xx zpsd3xxv hi-z per cs equations address or logic inputs, a16-a18 input (hi-z) input (hi-z) port pins chip select outputs, psd3xx, logic 1 per cs equations pc0-pc2 cs8-cs10, cmos zpsd3xx zpsd3xxv hi-z per cs equations table 8a. external psd signal states during and just after reset note: 1. signal is valid immediately after reset for psd3xx and zpsd3xx devices. zpsd3xxv devices need an additional 500 nsec after reset before signal is valid. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 25 12.0 control signals (cont.) internal internal signal signal state state during during component internal signal reset power-down cs0-cs10 logic 1 (inactive) per cs equations csadin, csadout1, per equations pad a and pad b csadout2, logic 0 (inactive) for each csioport, internal signal es0-es7, rs0 all registers in csioport address space, including: 3 direction logic 0 in all bit of logic 0 until 3 data n/a all registers changed by mcu 3 page 3 pmr (turbo bit, zpsd3xx only) table 8b. internal psd signal states during and just after reset note: n/a = not applicable reset low v ih reset high zpsd3xxv is operational 500 ns 500 ns v il figure 8. the reset cycle (reset) (zpsd3xxv versions) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 26 13.0 program/data space and the 8031 this section only applies to users who have an 8031 or compatible mcu that outputs a signal such as psen when accessing program space. if this applies to you, be aware of the following: o the psd3xx can be configured using psdsoft such that the eprom is either 1) accessed by psen only (figure 10); or 2) accessed by psen or rd (figure 9). the default is psen only unless changed in psdsoft. o the sram and i/o ports (including csioport) can not be placed in program space only. by default, they are in data space only (figure 10). however, the sram may be placed in program and data space, as shown in figure 9. figure 9. combined address space internal oe oe oe cs cs cs rd address psen i/o ports pad sram * eprom internal oe oe oe cs cs cs rd address psen i/o ports pad sram * eprom figure 10. 8031-compatible separate code and data address spaces * not available on ??versions. * not available on ??versions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 27 14.0 system applications in figure 11, the psd3xx is configured to interface with intels 80c31, which is a 16-bit address/8-bit data bus microcontroller. its data bus is multiplexed with the low-order address byte. the 80c31 uses signals rd to read from data memory and psen to read from code memory. it uses wr to write into the data memory. it also uses active high reset and ale signals. the rest of the configuration bits, as well as the unconnected signals, are application specific, and thus, user dependent. microcontroller 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 1 13 3 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale txd rxd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 a19/csi 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 rd wr/v pp bhe/psen ale reset gnd psd3xx 80c31 34 12 v cc 44 0.1? reset note: reset to the psd3xx must be the output of a reset chip or buffer. if reset to the 80c31 is the output of an rc circuit, a separate buffered rc reset to the psd3xx (shorter than the 80c31 rc reset) must be provided to avoid a race condition. figure 11. psd3xx interface with intels 80c31 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 28 14.0 system applications (cont.) in figure 12, the psd3xx is configured to interface with motorolas 68hc11, which is a 16-bit address/8-bit data bus microcontroller. its data bus is multiplexed with the low-order address byte. the 68hc11 uses e and r/w signals to derive the read and write strobes. it uses the address strobe (as) for the address latch pulse. reset is an active-low signal. the rest of the configuration bits, as well as the unconnected signals, are specific, and thus, user dependent. microcontroller 20 21 22 23 24 25 43 45 47 49 44 46 48 50 34 33 32 31 30 29 28 27 52 51 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 13 3 1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 e r/w as reset xirq irq modb moda pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 a19/csi 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 5 6 4 17 18 19 2 3 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 pd0 pd1 pd2 pd3 pd4 pd5 pe0 pe1 pe2 pe3 pd4 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vrh vrl ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 e r/w/v pp as reset bhe/psen gnd reset psd3xx 34 12 v cc v cc 68hc11 xtal extal 44 0.1? figure 12. psd3xx interface with motorolas 68hc11 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 29 14.0 system applications (cont.) in figure 13, the psd3xx is configured to work directly with intels 80c196kb microcontroller, which is a 16-bit address/16-bit data bus processor. the address and data lines multiplexed. the psd3xx is configured to use pc0, pc1, pc2, and a19/csi as logic inputs. these signals are independent of the ale pulse (latch-transparent). they are used as four general-purpose inputs that take part in the pad equations. port a is configured to work in track mode, in which (for certain conditions) pa0?a7 tracks lines ad0/a0?d7/a7. port b is configured to generate cs0?s7. in this example, pb2 serves as a wait signal that slows down the 80c196kb during the access of external peripherals. these 8-bit wide peripherals are connected to the shared bus of port a. the wait signal also drives the buswidth input of the microcontroller, so that every external peripheral cycle becomes an 8-bit data bus cycle. pb3 and pb4 are open-drain output signals; thus, they are pulled up externally. 67 68 36 nmi rxd txd + 5v rst 66 xtal1 ad [ 0 ..15 ] ad [ 0 ..15 ] xtal2 3 43 64 14 16 nmi ready buswidth cde reset 6 5 7 4 11 10 8 9 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 18 17 15 44 42 39 33 38 p2.0/txd p2.1/rxd p2.2/exint p2.3/t2clk p2.4/t2rst p2.5/pwm p2.6/ t2 up/dn p2.7/ t2 captr ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 ad6/a6 ad7/a7 ad8/a8 ad9/a9 ad10/a10 ad11/a11 ad12/a12 ad13/a13 ad14/a14 ad15/a15 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 1 2 22 13 3 pc0 pc1 pc2 a19/csi bhe /psen wr/v pp rd ale reset 24 25 26 27 hsi.0 hsi.1 hsi.2/hso.4 hsi.3/hso.5 13 37 12 2 vref vpp angnd ea 19 20 21 22 23 30 31 32 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 65 41 40 61 62 63 28 29 34 35 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/ad0 p3.1/ad1 p3.2/ad2 p3.3/ad3 p3.4/ad4 p3.5/ad5 p3.6/ad6 p3.7/ad7 p4.0/ad8 p4.1/ad9 p4.2/ad10 p4.3/ad11 p4.4/ad12 p4.5/ad13 p4.6/ad14 p4.7/ad15 clkout bhe / wrh wr / wrl rd ale /adv inst hso.0 hso.1 hso.2 hso.3 0.1? 0.1? four general purpose inputs gnd gnd 12 34 +5v +5v +5v 4.7k w 4.7k w 0.1? ale wait shared bus port 1 i/o pins 44 v cc v cc v ss v ss address/data multiplexed bus 80c196kb psd3xx figure 13. psd3xx interface with intels 80c196kb obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 30 15.0 security mode security mode in the psd3xx locks the contents of pad a, pad b, and all the configuration bits. the eprom, optional sram, and i/o contents can be accessed only through the pad. the security mode must be set by psdsoft prior to run-time. the security bit can only be erased on the uv parts using a full-chip erase. if security mode is enabled, the contents of the psd3xx can not be uploaded (copied) on a device programmer. 16.0 power management psds from all psd3xx families use zero-power memory techniques that place memory into standby mode between mcu accesses. the memory becomes active briefly after an address transition, then delivers new data to the outputs, latches the outputs, and returns to standby. this is done automatically and the designer has to do nothing special to benefit from this feature. in addition to the benefits of zero-power memory technology, there are ways to gain addi- tional savings. the following factors determine how much current the entire psd device uses: use of csi (chip select input) setting of the cmiser bit setting of the turbo bit (zpsd only) the number of product terms used in the pad the composite frequency of the input signals to the pad the loading on i/o pins. the total current consumption for the psd is calculated by summing the currents from memory, pad logic, and i/o pins, based on your design parameters and the power management options used. 16.1 csi input driving the csi pin inactive (logic 1) disables the inputs of the psd and forces the entire psd to enter power-down mode, independent of any transition on the mcu bus (address and control) or other psd inputs. during this time, the psd device draws only standby current (micro-amps). alternately, driving a logic 0 on the csi pin returns the psd to normal operation. see tables 7a and 7b for information on signal states during power-down mode. the csi pin feature is available only if enabled in the psdsoft configuration utility. 16.2 cmiser bit in addition to power savings resulting from the zero-power technology used in the memory, the cmiser feature saves even more power under certain conditions. savings are significant when the psd is configured for an 8-bit data path because the cmiser feature turns off half of the array when memory is being accessed (the memory is divided internally into odd and even arrays). see the dc characteristics table for current usage related to the cmiser bit. you should keep the following in mind when using this bit: setting of this bit is accomplished with psdsoft at the design stage, prior to run-time. memory access times are extended by 10 nsec for standard voltage (non-v) devices, and 20 nsec for low voltage (v) devices. eprom access: although cmiser offers significant power savings in 8-bit mode (~50%), cmiser contributes no additional power savings when the psd is configured for 16-bits. sram access: cmiser reduces power consumption of psds configured for either 8-bit or 16-bit operation. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 31 16. power management (cont.) 16.3 turbo bit (zpsd only) the turbo bit is controlled by the mcu at run-time and is accessed through bit zero of the power management register (pmr). the pmr is located in csioport space at offset 10h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** *** turbo bit 1= off 1= off 1= off 1= off 1= off 1= off 1= off 1= off power management register (pmr) * future configuration bits are reserved and should be set to one when writing to this register. the default value at reset of all bits in the pmr is logic 0, which means the turbo feature is enabled. the pad logic (pad a and pad b) of the psd will operate at full speed and full power. when the turbo bit is set to logic 1, the turbo feature is disabled. when disabled, the pad logic will draw only standby current (micro-amps) while no pad inputs change. whenever there is a transition on any pad input (including mcu address and control signals), the pad logic will power up and will generate new outputs, latch those outputs, then go back to standby mode. keep in mind that the signal propagation delay through the pad logic increases by 10 nsec for non-v devices, and 20 nsec for v devices while in non-turbo mode. use of the turbo bit does not affect the operation or power consumption of memory. tremendous power savings are possible by setting the turbo bit and going into non-turbo mode. this essentially reduces the dc power consumption of the pad logic to zero. it also reduces the ac power consumption of pad logic when the composite frequency of all pad inputs change at a rate less than 40 mhz for non-v devices, and less than 20 mhz for v devices. use figures 14 and 15 to calculate ac and dc current usage in the pad with the turbo bit on and off. you will need to know the number of product terms that are used in your design and you will have to calculate the composite frequency of all signals entering the pad logic. 16.4 number of product terms in the pad logic the number of product terms used in your design relates directly to how much current the pads will draw. therefore, minimizing this number will be in your best interest if power is a concern for you. basically, the amount of product terms your design will use is based on the following (see figure 4): each of the eprom block selects, es0-es7 uses one product term (for a total of 8). the csioport select uses one product term. if your part has sram (non-r versions), the sram select rs0 uses one product term. the track mode control signals (csadin, csadout1, and csadout2) each use one product term if you use these signals. port b, pins pb0-pb3 are allocated four product terms each if used as outputs. port b, pins pb4-pb7 are allocated two product terms each if used as outputs. port c, pins pc0-pc2 are allocated one product term each if used as outputs. given the above product term allocation, keep the following points in mind when calculating the total number of product terms your design will require: 1) the eprom block selects, csioport select, and sram select will use a product term whether you use these blocks or not. this means you start out with 10 product terms, and go up from there. 2) for port b, if you use a pin as an output and your logic equation requires only one product term, you still have to include all the available product terms for that pin for power consumption, even though only one product term is specified. for example, if the output equation for pin pb0 uses just one product term, you will have to count pb0 as contributing four product terms to the overall count. with this in mind, you should use port c for the outputs that only require one product term and pb4-7 for outputs that require two product terms. use pins pb0-3 if you need outputs requiring more than two product terms or you have run out of outputs. 3) the following psd functions do not consume product terms: mcu i/o mode, latched address output, and pad inputs (logic or address). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 32 16.0 power management (cont.) 16.5 composite frequency of the input signals to the pad logic the composite frequency of the input signals to the pads is calculated by considering all transitions on any pad input signal (including the mcu address and control inputs). once you have calculated the composite frequency and know the number of product terms used, you can determine the total ac current consumption of the pad by using figure 14 or figure 15. from the figures, notice that the dc component (f = 0 mhz) of pad current is essentially zero when the turbo feature is disabled, and that the ac component increases as frequency increases. when the turbo feature is disabled, the pad logic can achieve low power consumption by becoming active briefly, only when inputs change. for standard voltage (non-v) devices, the pad logic will stay active for 25 nsec after it detects a transition on any input. if there are more transitions on any pad input within the 25 nsec period, these transitions will not add to power consumption because the pad logic is already active. this effect helps reduce the overall composite frequency value. in other words, narrowly spaced groups of transitions on input signals may count as just one transition when estimating the composite frequency. note that the ?nee?frequency in figure 14 is 40 mhz, which means that the pad will consume less power only if the composite frequency of all pad inputs is less than 40 mhz. when the composite frequency is above 40 mhz, the pad logic never gets a chance to shut down (inputs are spaced less than 25 nsec) and no power savings can be achieved. figure 15 is for low-voltage devices in which the ?nee?frequency is 20 mhz. take the following steps to calculate the composite frequency: 1) determine your highest frequency input for either pad a or pad b. 2) calculate the period of this input and use this period as a basis for determining the composite frequency. 3) examine the remaining pad input signals within this base period to determine the number of distinct transitions. 4) signal transitions that are spaced further than 25 nsec apart count as a distinct transition (50 nsec for low-voltage v devices). signal transitions spaced closer than 25 nsec count as the same transition. 5) count up the number of distinct transitions and divide that into the value of the base period. 6) the result is the period of the composite frequency. divide into one to get the composite frequency value. unfortunately, this procedure is complicated and usually not deterministic since different inputs may be changing in various cycles. therefore, we recommend you think of the situation that has the most activity on the inputs to the pld and use this to calculate the composite frequency. then you will have a number that represents your best estimate at the worst case scenario. since this is a complicated process, the following example should help. example composite frequency calculation suppose you had the following circuit: 80c31 (12 mhz crystal) psd3xx pa pb pc ad0-ad7 latched address output (la0 - la7) a8-a15 ale rd wr psen csi 3 inputs: int, sel, rdy 5 mcu i/o outputs 3 chip-select outputs obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 33 all the inputs shown, except csi, go to the pad logic. these signals must be taken into consideration when calculating the composite frequency. before we make the calculation, lets establish the following conditions: the input with the highest frequency is ale, which is 2 mhz. so our base period is 500 nsec for this example. only the address information from the multiplexed signals ad0-ad7 reach the pad logic because of the internal address latch. signal transitions from data on ad0-ad7 do not reach the pads. the three inputs (int, sel, or rdy) change state very infrequently relative to the 80c31 bus signals. now, lets assume the following is a snapshot in time of all the input signals during a typical 80c31 bus cycle. we?l use a code fetch as an example since that happens most often. 16.0 power management (cont.) one typical 80c31 bus cycle (2 mhz, 500 nsec) ale psen ad0-ad7 a8-a15 int sel rdy four distinct transitions < 25 nsec addr data 1 2 3 the calculation of the composite frequency is as follows: there are four distinct transitions (first four dotted lines) within the base period of 500 nsec. these first four transitions all count toward the final composite frequency. the transition at (1) in the diagram does not count as a distinct transition because it is within 25 nsec of a neighboring transition (use 50 nsec for a zpsd3xxv device). transition (2) above does not add to the composite frequency because only the internally latched address signals reach the pads, the data signal transitions do not. the transition at (3) just happens to appear in this snapshot, but its frequency is so low that it is not a significant contributor to the overall composite frequency, and will not be used. divide the 500 nsec base period by the four (distinct transitions), yielding 125 nsec. 1/125 nsec = 8 mhz. use 8 mhz as the composite frequency of pad inputs when calculating current consumption. (see the next section for a sample current calculation.) 16.6 loading on i/o pins a final consideration when calculating the current usage for the entire psd device is the loading on i/o pins. all specifications for psd current consumption in this document assume zero current flowing through psd i/o pins (including adio). i/o current is dictated by the individual design implementation, and must be calculated by the designer. be aware that i/o current is a function of loading on the pins and the frequency at which the signals toggle. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 34 conditions part used = zpsd3xx (v cc = 5.0 v) mcu ale clock frequency = 2.0 mhz composite zpld input frequency = 8.0 mhz (see example in above section) % eprom access = 80% % sram access = 15% % i/o access = 5% %time csi is high (standby mode) = 90% %time csi is low (normal operation mode) = 10% # product terms used (see previous section) = 13 (13/40 = 33%) turbo bit = off (turbo mode disabled) cmiser bit = on mcu bus configuration = 8-bit multiplexed bus mode calculation (based on typical ac and dc currents) i cc total = istandby x % time csi is high + [ i cc (ac) + i cc (dc) ] x % time csi is low. = istandby x % time csi is high + [% eprom access x 0.8 ma/mhz x freq. of ale + % sram x 1.4 ma/mhz x freq of ale + zpld ac current (figure 14: 13 pts, 8 mhz, non-turbo) ] x % time csi is low = 10 ? x 0.9 + (0.8 x 0.8 ma/mhz x 2 mhz + 0.15 x 1.4 ma/mhz x 2 mhz + 5.0 ma) x 0.1 = 9.0 ? + (1.28 ma + 0.42 ma + 5.0 ma) x 0.1 = 679 ?, based on the system operating in standby 90% of the time once you have read the ?ower management?section, you should be able to calculate power. the following is a sample power calculation: 17. calculating power notes : 1. calculation is based on the assumption that i out = 0 ma (no i/o pin loading) 2. i cc (dc) is zero for all zpsd devices operating in non-turbo mode. 3. 13 product terms: 8 for eprom, 3 for chip selects, 1 for sram, 1 for csioport. 4. the 5% i/o access in the conditions section is when the mcu accesses csioport space. 5. standby mode can also be achieved without using the csi pin. the zpsd device will automatically go into standby while no inputs are changing on any pin, and turbo mode is disabled. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 35 17.0 calculating power (cont.) 0 0 5 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 45 i cc (ma composite frequency at pad inputs (mhz) 40 pt turbo 40 pt non -turbo 10 pt turbo 10 pt non -turbo figure 14. typical i cc vs. frequency for the pad (v cc = 5 v) 0 0 5 10 15 20 25 2 4 6 8 10 12 14 i cc (ma composite frequency at pad inputs (mhz) 40 pt turbo 40 pt non -turbo 10 pt turbo 10 pt non -turbo figure 15. typical i cc vs. frequency (v cc = 3 v) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 36 figure 18. normalized i cc (ac) (v cc = 3.0 v) figure 19. normalized access time (t6) (v cc = 3.0 v) figure 16. i ol vs. v ol (5 v 10%) figure 17. normalized i cc (dc vs. v cc ) (v cc = 3.0 v) 40 35 30 25 20 15 10 5 0 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 v ol (v) i ol (ma) temp. = 125? temp. = 25? 3.5 3.0 2.5 2.0 1.5 1.0 0.5 i cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc ( v ) 2.7 2.7 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 i cc (ac) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc ( v ) 2.7 1.1 1.05 1.0 0.95 0.9 0.85 0.8 0.75 0.7 0.65 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 access time v cc ( v ) zpsd3xxv zpsd3xxv zpsd3xxv zpsd3xxv obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 37 symbol parameter condition min max unit t stg storage temperature cerdip ?65 + 150 ? plastic ?65 + 125 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp programming supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v 18.1 absolute maximum ratings 1 note: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. range temperature v cc v cc tolerance commercial 0 c to +70? + 3 v 1 , + 5 v 10% industrial 40 c to +85? + 3 v 1 , + 5 v 10% symbol parameter conditions min typ max unit v cc supply voltage zpsd versions, all speeds 4.5 5 5.5 v v cc supply voltage zpsd v versions only, 2.7 3.0 5.5 v all speeds 18.2 operating range 18.3 recommended operating conditions notes: 1. 3 v version available for zpsd3xxv devices only. symbol parameter conditions typical 2 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for wr/v pp or r/w/v pp )v pp = 0 v 18 25 pf notes: 1. this parameter is only sampled and is not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. 18.4 pin capacitance 1 18.0 specifications obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 38 notes: 1. cmos inputs: gnd 0.3 v or v cc 0.3v. 2. ttl inputs: v il 0.8 v, v ih 3 2.0 v. 3. i out = 0 ma. 4. csi/a19 is high and the part is in a power-down configuration mode. 5. all other cases include cmiser = on and 16-bit bus mode and cmiser = off and 8- or 16-bit bus mode. symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high-level input voltage 4.5 v < v cc > 5.5 v 2 v cc +.1 v v il low-level input voltage 4.5 v < v cc > 5.5 v 0.5 0.8 v i oh = 20 ?, v cc = 4.5 v 4.4 4.49 v v oh output high voltage i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v output low voltage i ol = 20 ?, v cc = 4.5 v 0.01 0.1 v v ol (see figure 16) i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v zpsd3xx 10 20 ? i sb standby supply current (notes 1,4) psd3xx standby supply current 50 100 ? i li input leakage current v ss < v in > v cc ? .1 1 ? i lo output leakage current .45 < v in > v cc ?0 5 10 ? zpld turbo mode = off, f = 0 mhz see i sb ? zpsd3xx zpld turbo mode = on, f = 0 mhz 0.5 1 ma/pt operating suppy current eprom, f = 0 mhz 0 0 ? i cc (dc) sram, f = 0 mhz 0 0 ? (note 3) pld, f = 0 mhz 0.5 1 ma/pt psd3xx eprom, f = 0 mhz 0 0 ? operating supply current sram, f = 0 mhz 0 0 ? zpld ac base see 1.0 ma/mhz fig. 14 eprom access cmiser = on and 8-bit bus mode 0.8 2.0 ma/mhz i cc (ac) ac adder all other cases (note 5) 1.8 4.0 ma/mhz (note 3) cmiser = on and 8-bit bus mode 1.4 2.7 ma/mhz sram access cmiser = on and 16-bit bus mode 2 4 ma/mhz ac adder cmiser = off 3.8 7.5 ma/mhz 18.5 ac/dc characteristics ?psd3xx/zpsd3xx (all 5 v devices) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 39 symbol parameter conditions min typ max unit v cc supply voltage all speeds 2.7 3 5.5 v v ih high-level input voltage 2.7 v < v cc > 5.5 v .7 v cc v cc +.5 v v il low-level input voltage 2.7 v < v cc > 5.5 v 0.5 .3 v cc v i oh = 20 ?, v cc = 2.7 v 2.6 2.69 v v oh output high voltage i oh = 1 ma, v cc = 2.7 v 2.3 2.4 v i ol = 20 ?, v cc = 2.7 v 0.01 0.1 v v ol output low voltage i ol = 4 ma, v cc = 2.7 v 0.15 0.45 v i sb standby supply current v cc = 3.0 v 1 5 a (notes 1,4) i li input leakage current v in = v cc or gnd ? .1 1 ? i lo output leakage current v out = v cc or gnd ? .1 1 a zpld turbo mode = off, f = 0 mhz, v cc = 3.0 v see i sb ? i cc (dc) operating supply current zpld turbo mode = on, (note 3) f = 0 mhz, v cc = 3.0 v 0.17 0.35 ma/pt eprom, f = 0 mhz, v cc = 3.0 v 00a zpld ac base see figure 15 (v cc = 3.0 v) see 0.5 mz/mhz fig. 15 cmiser = on and 8-bit bus eprom access mode (v cc = 3.0 v) 0.4 1 ma/mhz ac adder all other cases (note 5) i cc (ac) (v cc = 3.0 v) 0.9 1.7 ma/mhz (note 3) cmiser = on and 8-bit bus 0.7 1.4 ma/mhz mode (v cc = 3.0 v) sram access ac adder cmiser = on and 16-bit bus 1 2 ma/mhz mode (v cc = 3.0 v) cmiser = off (v cc = 3.0 v) 1.9 3.8 ma/mhz 18.6 ac/dc dc characteristics ? zpsd3xxv (3 v devices only) notes: 1. cmos inputs: gnd 0.3 v or v cc 0.3v. 2. ttl inputs: v il 0.8 v, v ih 3 2.0 v. 3. i out = 0 ma. 4. csi/a19 is high and the part is in a power-down configuration mode. 5. all other cases include cmiser = on and 16-bit bus mode and cmiser = off and 8- or 16-bit bus mode. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 40 -70 -90* -15 cmiser turbo symbol parameter on = off = unit min max min max min max add add t1 ale or as pulse width 18 20 40 0 0 ns t2 address set-up time 5 5 12 0 0 ns t3 address hold time 7 8 10 0 0 ns t4 leading edge of read to data active 00 0 00ns t5 ale valid to data valid 80 100 160 10 0 ns t6 address valid to data valid 70 90 150 10 0 ns t7 csi active to data valid 80 100 160 10 0 ns t8 leading edge of read to data valid 20 32 55 0 0 ns leading edge of read to data valid in 8031-based t8a architecture operating with 32 32 55 0 0 ns psen and rd in separate mode t9 read data hold time 0 0 0 0 0 ns t10 trailing edge of read to data high-z 20 32 35 0 0 ns trailing edge of ale or as t11 to leading edge of write 00 0 00ns t12 rd, e, psen, or ds pulse width 35 40 60 0 0 ns t12a wr pulse width 18 20 35 0 0 ns trailing edge of write or read t13 to leading edge of ale or as 55 5 00ns t14 address valid to trailing edge of write 70 90 150 0 0 ns csi active to trailing edge t15 of write 80 100 160 0 0 ns t16 write data set-up time 18 20 30 0 0 ns t17 write data hold time 5 5 10 0 0 ns t18 port to data out valid propagation delay 25 30 35 0 0 ns t19 port input hold time 0 0 0 0 0 ns t20 trailing edge of write to port output valid 30 40 50 0 0 ns t21 adi 1 or control to csoi 2 valid 6 20 6 25 6 35 0 10 ns t22 adi 1 or control to csoi 2 invalid 5 20 5 25 4 35 0 10 ns 18.7 timing parameters ? psd3xx/zpsd3xx (all 5 v devices) * -90 speed available only on industrial temperature versions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 41 -70 -90* -15 cmiser turbo symbol parameter on = off = unit min max min max min max add add track mode address propagation delay: 22 22 28 0 0 ns t23 csadout1 already true latched address outputs, port a 22 22 28 0 0 track mode address propagation delay: t23a csadout1 becomes true 33 33 50 0 10 ns during ale or as track mode trailing edge of t24 ale or as to address high-z 30 32 35 0 0 ns t25 track mode read propagation delay 27 29 35 0 0 ns t26 track mode read hold time 5 29 11 29 11 29 0 0 ns t27 track mode write cycle, data propagation delay 18 20 30 0 0 ns track mode write cycle, t28 write to data propagation delay 630830 940 0 10ns hold time of port a valid t29 during write csoi 2 trailing edge 22 2 00ns t30 csi active to csoi 2 active 8 37 9 40 9 50 0 0 ns t31 csi inactive to csoi 2 inactive 8 37 9 40 9 50 0 0 ns t32 direct pad input 3 as hold time 0 10 12 0 0 ns t33 r/w active to e or ds start 18 20 30 0 0 ns t34 e or ds end to r/w 18 20 30 0 0 ns t35 as inactive to e high 0 0 0 0 0 ns t36 address to leading edge of write 18 20 25 0 0 ns 18.7 timing parameters ? psd3xx/zpsd3xx (all 5 v devices) (cont.) notes: 1. adi = any address line. 2. csoi = any of the chip-select output signals coming through port b (cs0?s7) or through port c (cs8?s10). 3. direct pad input = any of the following direct pad input lines: csi/a19 as transparent a19, rd/e/ds, wr or r/w, transparent pc0?c2, ale (or as). 4. control signals rd/e/ds or wr or r/w. * -90 speed available only on industrial temperature versions. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 42 -15* -20 -25 cmiser turbo symbol parameter on = off = unit min max min max min max add add t1 ale or as pulse width 40 50 60 0 0 ns t2 address set-up time 12 15 20 0 0 ns t3 address hold time 10 15 20 0 0 ns t4 leading edge of read to data active 00 0 00ns t5 ale valid to data valid 170 200 250 20 0 ns t6 address valid to data valid 150 200 250 20 0 ns t7 csi active to data valid 160 200 250 20 0 ns t8 leading edge of read to data valid 45 50 60 0 0 ns leading edge of read to data valid in 8031-based t8a architecture operating with 65 70 80 0 0 ns psen and rd in separate mode t9 read data hold time 0 0 0 0 0 ns t10 trailing edge of read to data high-z 45 50 55 0 0 ns trailing edge of ale or as t11 to leading edge of write 00 0 00ns t12 rd, e, psen, or ds pulse width 60 75 85 0 0 ns t12a wr pulse width 35 45 55 0 0 ns trailing edge of write or read t13 to leading edge of ale or as 55 5 00ns t14 address valid to trailing edge of write 150 200 250 0 0 ns csi active to trailing edge t15 of write 160 200 250 0 0 ns t16 write data set-up time 30 40 50 0 0 ns t17 write data hold time 10 12 15 0 0 ns t18 port to data out valid propagation delay 45 50 60 0 0 ns t19 port input hold time 0 0 0 0 0 ns t20 trailing edge of write to port output valid 50 60 70 0 0 ns t21 adi 1 or control to csoi 2 valid 6 50 5 55 5 60 0 20 ns t22 adi 1 or control to csoi 2 invalid 4 50 4 55 4 60 0 20 ns 18.8 timing parameters ? zpsd3xxv (3 v devices only) * -15 speed available only on zpsd311v. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 43 notes: 1. adi = any address line. 2. csoi = any of the chip-select output signals coming through port b (cs0?s7) or through port c (cs8?s10). 3. direct pad input = any of the following direct pad input lines: csi/a19 as transparent a19, rd/e/ds, wr or r/w, transparent pc0?c2, ale (or as). 4. control signals rd/e/ds or wr or r/w. * -15 speed available only on zpsd311v. -15* -20 -25 cmiser turbo symbol parameter on = off = unit min max min max min max add add track mode address propagation delay: 50 60 60 0 0 ns t23 csadout1 already true latched address outputs, port a 50 60 60 0 0 track mode address propagation delay: t23a csadout1 becomes true 70 80 90 0 20 ns during ale or as track mode trailing edge of t24 ale or as to address high-z 50 60 60 0 0 ns t25 track mode read propagation delay 45 55 60 0 0 ns t26 track mode read hold time 10 70 10 70 10 70 0 0 ns t27 track mode write cycle, data propagation delay 45 55 60 0 0 ns track mode write cycle, t28 write to data propagation delay 865875 880 0 20ns hold time of port a valid t29 during write csoi 2 trailing edge 23 3 00ns t30 csi active to csoi 2 active 9 70 9 80 9 90 0 0 ns t31 csi inactive to csoi 2 inactive 9 70 9 80 9 90 0 0 ns t32 direct pad input 3 as hold time 0 0 0 0 0 ns t33 r/w active to e or ds start 30 40 50 0 0 ns t34 e or ds end to r/w 30 40 50 0 0 ns t35 as inactive to e high 0 0 0 0 0 ns t36 address to leading edge of write 30 35 40 0 0 ns 18.8 timing parameters ? zpsd3xxv (3 v devices only) (cont.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
18.9 timing diagrams for all psd3xx parts figure 20. timing of 8-bit multiplexed address/data bus using rd, wr (psd3x1) 18 data valid csi/a19 as csi data in 8 12 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 13 32 5 2 16 17 12a 19 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs a0/ad0- a7/ad7 active low ale active high ale rd/e as rd bhe/psen as psen wr/v pp or rw as wr any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 36 see referenced notes on page 64. psd3xx family 44 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 45 figure 21. timing of 8-bit multiplexed address/data bus using rd, wr (psd3x2/3x3) 18 data valid csi/a19 as csi data in 8 12 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 13 32 5 2 16 17 12a 19 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs a0/ad0- a7/ad7 active low ale active high ale rd/e/ds as rd bhe/psen as psen wr/v pp or rw as wr any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 36 see referenced notes on page 64 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 46 figure 22. timing of 8-bit multiplexed address/data bus using r/w, e or r/w, ds (psd3x1) 18 33 34 36 19 data valid csi/a19 as csi data in 8 12 5 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 33 13 2 16 17 12 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs a0/ad0- a7/ad7 active low as active high as rd/e as e wr/v pp or r/w as r/w any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 34 35 35 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 47 figure 23. timing of 8-bit multiplexed address/data bus using r/w e or r/w, ds (psd3x2/3x3) 18 33 34 36 19 data valid csi/a19 as csi data in 8 12 5 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 4 33 13 2 16 17 12 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs a0/ad0- a7/ad7 active low as active high as rd/e/ds as e wr/v pp or r/w as r/w any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 34 35 rd/e/ds as ds 35 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 48 figure 24. timing of 16-bit multiplexed address/data bus using rd, wr (psd3x1) 18 36 4 19 data valid csi/a19 as csi 12 5 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 8 13 2 16 17 12a 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs data in a0/ad0- a15/ad15 active low ale active high ale rd/e as rd bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 wr/v pp or r/w as wr 32 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 49 figure 25. timing of 16-bit multiplexed address/data bus using rd, wr (psd3x2/3x3) 18 36 4 19 data valid csi/a19 as csi 12 5 1 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 8 13 2 16 17 12a 13 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs data in a0/ad0- a15/ad15 active low ale active high ale rd/e/ds as rd bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 11 wr/v pp or r/w as wr 32 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 50 figure 26. timing of 16-bit multiplexed address/data bus using r/w, e or r/w, ds (psd3x1) 18 19 33 data valid csi/a19 as csi 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 35 13 4 2 16 17 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs data in a0/ad0- a15/ad15 active low as active high as bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 35 34 34 33 8 12 5 12 13 as e rd/e as e as e wr/v pp or r/w as r/w 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 51 figure 27. timing of 16-bit multiplexed address/data bus using r/w, e or r/w, ds (psd3x2/3x3) 18 19 33 data valid csi/a19 as csi 1 32 7 15 32 32 14 14 6 6 10 9 address a address b 2 3 35 13 4 2 16 17 20 23 23 address a address b input input output output read cycle write cycle stable input stable input direct (1) pad input multiplexed (2) inputs data in a0/ad0- a15/ad15 active low as active high as bhe/psen as bhe any of pa0-pa7 as i/o pin any of pa0-pa7 pins as address outputs any of pb0-pb7 as i/o pin 1 3 35 34 34 33 8 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 52 figure 28. timing of 8-bit non-multiplexed address/data bus using rd, wr (psd3x1) 18 8 19 data valid csi/a19 as csi 12 5 1 7 15 32 14 14 6 6 10 9 2 3 4 32 13 2 16 17 12a 13 20 input output read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input pc0-pc2, csi/a19 as multiplexed inputs data in pa0-pa7 active low ale active high ale rd/e as rd any of pb0-pb7 as i/o pin 1 3 11 32 32 wr/v pp or r/w as wr 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 53 figure 29. timing of 8-bit non-multiplexed address/data bus using rd, wr (psd3x2/3x3) 18 8 19 data valid csi/a19 as csi 12 5 1 7 15 32 14 14 6 6 10 9 2 3 4 32 13 2 16 17 12a 13 20 input output read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input multiplexed (2) inputs data in pa0-pa7 active low ale active high ale rd/e/ds as rd any of pb0-pb7 as i/o pin 1 3 11 32 32 wr/v pp or r/w as wr 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 54 figure 30. timing of 8-bit non-multiplexed address/data bus using r/w, e or r/w, ds (psd3x1) 8 data valid csi/a19 as csi 1 7 15 32 32 14 14 6 6 10 9 2 3 35 32 32 2 16 17 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input pc0-pc2, csi/a19 as multiplexed inputs data in pa0-pa7 active low ale active high ale 1 3 35 18 12 19 33 13 20 input output any of pb0-pb7 as i/o pin 4 34 34 33 12 13 rd/e as e as e as e as e wr/v pp or r/w as r/w 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 55 figure 31. timing of 8-bit non-multiplexed address/data bus using r/w, e or r/w, ds (psd3x2/3x3) 8 data valid csi/a19 as csi 1 7 15 32 32 14 14 6 6 10 9 2 3 35 32 32 2 16 17 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input multiplexed (2) inputs data in pa0-pa7 active low ale active high ale 1 3 35 36 18 19 33 13 20 input output any of pb0-pb7 as i/o pin 4 34 34 33 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 56 figure 32. timing of 16-bit non-multiplexed address/data bus using rd, wr (psd3x1) 8 csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input pc0-pc2, csi/a19 as multiplexed inputs data in active low ale active high ale 1 3 3 2 2 11 13 12 12a 13 rd/e as rd wr/v pp or r/w as wr data valid 14 10 9 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 57 figure 33. timing of 16-bit non-multiplexed address/data bus using rd, wr (psd3x2/3x3) 8 csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input multiplexed (2) inputs data in active low ale active high ale 1 3 3 2 2 11 13 12 5 12a 13 rd/e/ds as rd wr/v pp or r/w as wr data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 58 figure 34. timing of 16-bit non-multiplexed address/data bus using r/w, e or r/w, ds (psd3x1) csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 35 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input pc0-pc2, csi/a19 as multiplexed inputs data in active low as active high as 1 3 3 8 2 2 35 33 data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 13 34 34 33 12 13 rd/e as e as e as e as e wr/v pp or r/w as r/w 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 59 figure 35. timing of 16-bit non-multiplexed address/data bus using r/w, e or r/w, ds (psd3x2/3x3) csi/a19 as csi 1 32 7 15 32 32 14 6 6 4 35 32 read cycle write cycle stable input stable input a0/ad0- a15/ad15 as a0-a15 stable input stable input direct (1) pad input multiplexed (2) inputs data in active low as active high as 1 3 3 8 2 2 35 33 data valid 14 10 9 pa0-pa7 (low byte) data in data valid 17 16 pb0-pb7 (high byte) bhe/psen as bhe 13 34 34 33 12 5 12 13 rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w rd/e/ds as ds 36 see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 60 figure 36. chip-select output timing 30 21 31 a19/csi as csi direct pad (1) input multiplexed (2) pad inputs csoi (3,8) ale (multiplexed mode only) or ale (multiplexed mode only) 22 1 2 3 input stable see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 61 figure 37. port a as ad0ad7 timing (track mode) using rd, wr (psd3x1) 25 32 32 12a 28 24 11 data valid 12 1 32 32 24 26 2 address address 2 3 2 2 4 read cycle write cycle stable input stable input stable input stable input direct pad input (1,4) multiplexed pad inputs (5,7) a0/ad0- a7/ad7 or ale ale rd/e as rd wr/v pp or r/w as wr 1 3 27 pa0-pa7 29 csoi (3,6) data in data out written data 23 adr out 23 adr out see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 62 figure 38. port a as ad0ad7 timing (track mode) using rd, wr (psd3x2/3x3) 25 32 32 12a 28 24 11 data valid 12 1 32 32 24 26 2 address address 2 3 2 2 4 read cycle write cycle stable input stable input stable input stable input direct pad input (1,4) multiplexed pad inputs (5,7) a0/ad0- a7/ad7 or ale ale rd/e/ds as rd wr/v pp or r/w as wr 1 3 27 pa0-pa7 29 csoi (3,6) data in data out written data 23 adr out 23 adr out see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 63 figure 39. port a as ad0?d7 timing (track mode) using r/w, e or r/w, ds (psd3x1) 33 25 33 32 12 28 24 34 35 data valid 12 1 32 32 32 23 24 26 2 address address 2 3 2 35 read cycle write cycle stable input stable input stable input stable input direct pad input (1,4) multiplexed pad inputs (5,7) a0/ad0- a7/ad7 or as as rd/e as e as e as e as e wr/v pp or r/w as r/w 1 3 34 27 23 pa0-pa7 29 csoi (3,6) adr out data in data out written data adr out see referenced notes on page 64. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 64 figure 40. port a as ad0?d7 timing (track mode) using r/w, e or r/w, ds (psd3x2/3x3) 33 25 33 32 12 28 24 34 35 data valid 12 1 32 32 32 23 24 26 2 address address 2 3 2 35 read cycle write cycle stable input stable input stable input stable input direct pad input (1,4) multiplexed pad inputs (5,7) a0/ad0- a7/ad7 or as as rd/e/ds as e rd/e/ds as e rd/e/ds as e rd/e/ds as e wr/v pp or r/w as r/w 1 3 34 27 23 rd/e/ds as ds pa0-pa7 29 csoi (3,6) adr out data in data out written data adr out 1. direct pad input = any of the following direct pad input lines: csi/a19 as transparent a19, rd/e/ds, wr or r/w, transparent pc0?c2, ale in non-multiplexed modes. 2. multiplexed inputs: any of the following inputs that are latched by the ale (or as): a0/ad0?15/ad15, csi/a19 as ale dependent a19, ale dependent pc0?c2. 3. csoi = any of the chip-select output signals coming through port b (cs0?s7) or through port c (cs8?s10). 4. csadout1, which internally enables the address transfer to port a, should be derived only from direct pad input signals, otherwise the address propagation delay is slowed down. 5. csadin and csadout2, which internally enable the data-in or data-out transfers, respectively, can be derived from any combination of direct pad inputs and multiplexed pad inputs. 6. the write operation signals are included in the csoi expression. 7. multiplexed pad inputs: any of the following pad inputs that are latched by the ale (or as) in the multiplexed modes: a11/ad11?15/ad15, csi/a19 as ale dependent a19, ale dependent pc0?c2. 8. csoi product terms can include any of the pad input signals shown in figure 3, except for reset and csi. notes for timing diagrams obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 65 figure 41a. ac testing input/output waveform (5 v versions) figure 41b. ac testing input/output waveform (3 v versions) 3.0v 0v test point 1.5v device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) 0.9 v cc 0v test point 1.5v figure 42a. ac testing load circuit (5 v versions) device under test 2.0 v 400 w c l = 30 pf (including scope and jig capacitance) figure 42b. ac testing load circuit (3 v versions) 18.10 ac testing obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 66 44-pin 44-pin pin name pldcc/cldcc pqfp/ tqfp package package bhe/psen 1 39 wr/v pp or r/w 2 40 reset 3 41 pb7 4 42 pb6 5 43 pb5 6 44 pb4 7 1 pb3 8 2 pb2 9 3 pb1 10 4 pb0 11 5 gnd 12 6 ale or as 13 7 pa7 14 8 pa6 15 9 pa5 16 10 pa4 17 11 pa3 18 12 pa2 19 13 pa1 20 14 pa0 21 15 rd/e 22 16 ad0/a0 23 17 ad1/a1 24 18 ad2/a2 25 19 ad3/a3 26 20 ad4/a4 27 21 ad5/a5 28 22 ad6/a6 29 23 ad7/a7 30 24 ad8/a8 31 25 ad9/a9 32 26 ad10/a10 33 27 gnd 34 28 ad11/a11 35 29 ad12/a12 36 30 ad13/a13 37 31 ad14/a14 38 32 ad15/a15 39 33 pc0 40 34 pc1 41 35 pc2 42 36 a19/csi 43 37 v cc 44 38 19.0 pin assignments obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 67 figure 44. drawing m1 44 pin plastic quad flatpack (pqfp) (package type m) or drawing u1 44 pin plastic thin quad flatpack (tqfp) (package type u) 39 ad15/a15 38 ad14/a14 37 ad13/a13 36 ad12/a12 35 ad11/a11 34 gnd 33 ad10/a10 32 ad9/a9 31 ad8/a8 30 ad7/a7 29 ad6/a6 pb4 7 pb3 8 pb2 9 pb1 10 pb0 11 gnd 12 ale or as 13 pa7 14 pa6 15 pa5 16 pa4 17 pa3 18 pa2 19 pa1 20 pa0 21 rd/e 22 ad0/a0 23 ad1/a1 24 ad2/a2 25 ad3/a3 26 ad4/a4 27 ad5/a5 28 6 pb5 5 pb6 4 pb7 3 reset 2 wr/v or r/w 1 bhe/psen 44 v 43 a19/csi 42 pc2 41 pc1 40 pc0 pp cc pb4 pb3 pb2 pb1 pb0 gnd ale or as pa7 pa6 pa5 pa4 ad15/a15 ad14/a14 ad13/a13 ad12/a12 ad11/a11 gnd ad10/a10 ad9/a9 ad8/a8 ad7/a7 ad6/a6 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 pa3 pa2 pa1 pa0 rd/e ad0/a0 ad1/a1 ad2/a2 ad3/a3 ad4/a4 ad5/a5 pb5 pb6 pb7 reset wr/v pp or r/w bhe/psen v cc a19/csi pc2 pc1 pc0 44 43 42 41 40 39 38 37 36 35 34 (top view) 20.0 package information figure 43. drawing j2 44 pin plastic leaded chip carrier (pldcc) without window (package type j) or drawing l4 44 pin ceramic leaded chip carrier (cldcc) with window (package type l) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 68 family: plastic leaded chip carrier millimeters inches symbol min max notes min max notes a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 3.76 3.96 0.148 0.156 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.262 0.0097 0.0103 d 17.40 17.65 0.685 0.695 d1 16.51 16.61 0.650 0.654 d2 14.99 16.00 0.590 0.630 d3 12.70 reference 0.500 reference e 17.40 17.65 0.685 0.695 e1 16.51 16.61 0.650 0.654 e2 14.99 16.00 0.590 0.630 e3 12.70 reference 0.500 reference e1 1.27 reference 0.050 reference n44 44 030195r6 drawing j2 ? 44-pin plastic leaded chip carrier (pldcc) (package type j) d3 b a1 a2 e1 e d2 a e2 c d d1 44 1 2 3 e3 e1 b1 21.0 package drawings obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 69 family: ceramic leaded chip carrier ? cerquad millimeters inches symbol min max notes min max notes a 3.94 4.57 0.155 0.180 a1 2.29 2.92 0.090 0.115 a2 3.05 3.68 0.120 0.145 b 0.43 0.53 0.017 0.021 b1 0.66 0.81 0.026 0.032 c 0.15 0.25 0.006 0.010 d 17.40 17.65 0.685 0.695 d1 16.31 16.66 0.642 0.656 d2 14.73 16.26 0.580 0.640 d3 12.70 reference 0.500 reference e 17.40 17.65 0.685 0.695 e1 16.31 16.66 0.642 0.656 e2 14.73 16.26 0.580 0.640 e3 12.70 reference 0.500 reference e1 1.27 reference 0.050 reference n44 44 030195r8 drawing l4 ? 44-pin pocketed ceramic leaded chip carrier (cldcc) ? cerquad (package type l) d3 b1 b a1 a e1 e 44 d2 a2 c 1 2 3 e2 d1 d e3 e1 view a commercial and industrial packages include the lead pocket on the underside of the package but military packages do not. view a obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 70 drawing m1 ? 44-pin plastic quad flatpack (pqfp) (package type m) b e1 e 1 d3 e3 d1 d l a 2 3 44 a2 a a1 c index mark e1 standoff: 0.10 mm min 0.25 mm max family: plastic quad flatpack (pqfp) millimeters inches symbol min max notes min max notes a 0 7 0 7 a 2.35 0.092 a1 1.075 reference 0.042 reference a2 1.95 2.10 0.077 0.083 b 0.30 0.45 0.012 0.018 c 0.13 0.23 0.005 0.009 d 13.20 0.520 d1 10.00 0.394 d3 8.00 reference 0.315 reference e 13.20 0.520 e1 10.00 0.394 e3 8.00 reference 0.315 reference e1 0.80 reference 0.031 reference l 0.73 1.03 0.029 0.040 n44 44 030195r4 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 71 drawing u1 ? 44-pin plastic thin quad flatpack (tqfp) (package type u) b e1 e 1 d3 e3 d1 d l a 2 3 44 a2 a a1 c index mark e1 standoff: 0.05 mm min lead coplanarity: 0.102 mm max. family: plastic thin quad flatpack (tqfp) millimeters inches symbol min max notes min max notes a 0 8 0 8 a 1.60 0.063 a1 0.54 0.74 0.021 0.029 a2 1.15 1.55 0.045 0.061 b 0.35 reference 0.014 reference c 0.09 0.20 0.004 0.008 d 15.75 16.25 0.620 0.640 d1 13.90 14.10 0.547 0.555 d3 10.00 reference 0.394 reference e 15.75 16.25 0.620 0.640 e1 13.90 14.10 0.547 0.555 e3 10.00 reference 0.394 reference e1 1.00 reference 0.039 reference l 0.35 0.65 0.014 0.026 n44 44 030195r4 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
st part # mcu plds/decoders i/o memory other psd zpsd zpsd 8-bit 16-bit interface inputs product pld page ports open eprom sram peripheral security @ @ @ data data terms outputs reg. drain mode 5 v 5 v 2.7 v psd311r zpsd311r x std 14 40 11 19 x 256kb x x psd301r zpsd301r x x std 14 40 11 19 x 256kb x x psd312r zpsd312r x std 18 40 11 x 19 x 512kb x x psd302r zpsd302r x x std 18 40 11 x 19 x 512kb x x psd313r zpsd313r x std 18 40 11 x 19 x 1024kb x x psd303r zpsd303r x x std 18 40 11 x 19 x 1024kb x x psd311 zpsd311 zpsd311v x std 14 40 11 19 x 256kb 16kb x x psd301 zpsd301 zpsd301v x x std 14 40 11 19 x 256kb 16kb x x psd312 zpsd312 zpsd312v x std 18 40 11 x 19 x 512kb 16kb x x psd302 zpsd302 zpsd302v x x std 18 40 11 x 19 x 512kb 16kb x x psd313 zpsd313 zpsd313v x std 18 40 11 x 19 x 1024kb 16kb x x psd303 zpsd303 zpsd303v x x std 18 40 11 x 19 x 1024kb 16kb x x psd3xx family 72 22.1 psd3xx family ? selector guide 22.0 psd3xx ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) - obsolet obsolete product(s) - obsolete product(s) - obsolet
psd3xx family 73 psd3xx ordering information (cont.) temperature (blank = commercial, i = industrial, m = military) package type speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) revision (blank = no revision) supply voltage (blank = 5v, v = 3 volt) base part number - see selector guide psd ( st programmable system device) fam. power down feature (blank = standard, z = zero power feature) z psd -a -20 j i 413a2 v 22.2 part number construction operating speed temperature part number (ns) package type range psd301-b-70j 70 44 pin pldcc comm? psd301-b-70l 70 44 pin cldcc comm? psd301-b-70m 70 44 pin pqfp comm? psd301-b-70u 70 44 pin tqfp comm? psd301-b-90ji 90 44 pin pldcc industrial psd301-b-90li 90 44 pin cldcc industrial psd301-b-90mi 90 44 pin pqfp industrial psd301-b-90ui 90 44 pin tqfp industrial psd301-b-15j 150 44 pin pldcc comm? psd301-b-15l 150 44 pin cldcc comm? psd301-b-15m 150 44 pin pqfp comm? psd301-b-15u 150 44 pin tqfp comm? psd301r-b-70j 70 44 pin pldcc comm? psd301r-b-90ji 90 44 pin pldcc industrial psd301r-b-15j 150 44 pin pldcc comm? 22.3 ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 74 operating speed temperature part number (ns) package type range psd302-b-70j 70 44 pin pldcc comm? psd302-b-70l 70 44 pin cldcc comm? psd302-b-70m 70 44 pin pqfp comm? psd302-b-70u 70 44 pin tqfp comm? psd302-b-90ji 90 44 pin pldcc industrial psd302-b-90li 90 44 pin cldcc industrial psd302-b-90mi 90 44 pin pqfp industrial psd302-b-90ui 90 44 pin tqfp industrial psd302-b-15j 150 44 pin pldcc comm? psd302-b-15l 150 44 pin cldcc comm? psd302-b-15m 150 44 pin pqfp comm? psd302-b-15u 150 44 pin tqfp comm? psd302r-b-70j 70 44 pin pldcc comm? psd302r-b-90ji 90 44 pin pldcc industrial psd302r-b-15j 150 44 pin pldcc comm? psd303-b-70j 70 44 pin pldcc comm? psd303-b-70l 70 44 pin cldcc comm? psd303-b-70m 70 44 pin pqfp comm? psd303-b-70u 70 44 pin tqfp comm? psd303-b-90ji 90 44 pin pldcc industrial psd303-b-90li 90 44 pin cldcc industrial psd303-b-90mi 90 44 pin pqfp industrial psd303-b-90ui 90 44 pin tqfp industrial psd303-b-15j 150 44 pin pldcc comm? psd303-b-15l 150 44 pin cldcc comm? psd303-b-15m 150 44 pin pqfp comm? psd303-b-15u 150 44 pin tqfp comm? psd303r-b-70j 70 44 pin pldcc comm? psd303r-b-90ji 90 44 pin pldcc industrial psd303r-b-15j 150 44 pin pldcc comm? psd311-b-70j 70 44 pin pldcc comm? psd311-b-70l 70 44 pin cldcc comm? psd311-b-70m 70 44 pin pqfp comm? psd311-b-70u 70 44 pin tqfp comm? psd311-b-90ji 90 44 pin pldcc industrial psd311-b-90li 90 44 pin cldcc industrial psd311-b-90mi 90 44 pin pqfp industrial psd311-b-90ui 90 44 pin tqfp industrial psd311-b-15j 150 44 pin pldcc comm? psd311-b-15l 150 44 pin cldcc comm? psd311-b-15m 150 44 pin pqfp comm? psd311-b-15u 150 44 pin tqfp comm? psd311r-b-70j 70 44 pin pldcc comm? psd311r-b-90ji 90 44 pin pldcc industrial psd311r-b-15j 150 44 pin pldcc comm? ordering information psd3xx ordering information (cont.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 75 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range psd312-b-70j 70 44 pin pldcc comm? psd312-b-70l 70 44 pin cldcc comm? psd312-b-70m 70 44 pin pqfp comm? psd312-b-70u 70 44 pin tqfp comm? psd312-b-90ji 90 44 pin pldcc industrial psd312-b-90li 90 44 pin cldcc industrial psd312-b-90mi 90 44 pin pqfp industrial psd312-b-90ui 90 44 pin tqfp industrial psd312-b-15j 150 44 pin pldcc comm? psd312-b-15l 150 44 pin cldcc comm? psd312-b-15m 150 44 pin pqfp comm? psd312-b-15u 150 44 pin tqfp comm? psd312r-b-70j 70 44 pin pldcc comm? psd312r-b-90ji 90 44 pin pldcc industrial psd312r-b-15j 150 44 pin pldcc comm? psd313-b-70j 70 44 pin pldcc comm? psd313-b-70l 70 44 pin cldcc comm? psd313-b-70m 70 44 pin pqfp comm? psd313-b-70u 70 44 pin tqfp comm? psd313-b-90ji 90 44 pin pldcc industrial psd313-b-90li 90 44 pin cldcc industrial psd313-b-90mi 90 44 pin pqfp industrial psd313-b-90ui 90 44 pin tqfp industrial psd313-b-15j 150 44 pin pldcc comm? psd313-b-15l 150 44 pin cldcc comm? psd313-b-15m 150 44 pin pqfp comm? psd313-b-15u 150 44 pin tqfp comm? psd313r-b-70j 70 44 pin pldcc comm? psd313r-b-90ji 90 44 pin pldcc industrial psd313r-b-15j 150 44 pin pldcc comm? ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 76 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range zpsd301-b-70j 70 44 pin pldcc comm? zpsd301-b-70l 70 44 pin cldcc comm? zpsd301-b-70m 70 44 pin pqfp comm? zpsd301-b-70u 70 44 pin tqfp comm? zpsd301-b-90ji 90 44 pin pldcc industrial zpsd301-b-90li 90 44 pin cldcc industrial zpsd301-b-90mi 90 44 pin pqfp industrial zpsd301-b-90ui 90 44 pin tqfp industrial zpsd301-b-15j 150 44 pin pldcc comm? zpsd301-b-15l 150 44 pin cldcc comm? zpsd301-b-15m 150 44 pin pqfp comm? zpsd301-b-15u 150 44 pin tqfp comm? zpsd301r-b-70j 70 44 pin pldcc comm? zpsd301r-b-90ji 90 44 pin pldcc industrial zpsd301r-b-15j 150 44 pin pldcc comm? zpsd301v-b-15j 150 44 pin pldcc comm? zpsd301v-b-15l 150 44 pin cldcc comm? zpsd301v-b-15u 150 44 pin tqfp comm? zpsd301v-b-20j 200 44 pin pldcc comm? zpsd301v-b-20ji 200 44 pin pldcc industrial zpsd301v-b-20l 200 44 pin cldcc comm? zpsd301v-b-20m 200 44 pin pqfp comm? zpsd301v-b-20mi 200 44 pin pqfp industrial zpsd301v-b-20u 200 44 pin tqfp comm? zpsd301v-b-20ui 200 44 pin tqfp industrial zpsd301v-b-25j 250 44 pin pldcc comm? zpsd301v-b-25l 250 44 pin cldcc comm? zpsd301v-b-25m 250 44 pin pqfp comm? zpsd301v-b-25u 250 44 pin tqfp comm? zpsd302-b-70j 70 44 pin pldcc comm? zpsd302-b-70l 70 44 pin cldcc comm? zpsd302-b-70m 70 44 pin pqfp comm? zpsd302-b-70u 70 44 pin tqfp comm? zpsd302-b-90ji 90 44 pin pldcc industrial zpsd302-b-90li 90 44 pin cldcc industrial zpsd302-b-90mi 90 44 pin pqfp industrial zpsd302-b-90ui 90 44 pin tqfp industrial zpsd302-b-15j 150 44 pin pldcc comm? zpsd302-b-15l 150 44 pin cldcc comm? zpsd302-b-15m 150 44 pin pqfp comm? zpsd302-b-15u 150 44 pin tqfp comm? zpsd302r-b-70j 70 44 pin pldcc comm? zpsd302r-b-90ji 90 44 pin pldcc industrial zpsd302r-b-15j 150 44 pin pldcc comm? ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 77 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range zpsd302v-b-20j 200 44 pin pldcc comm? zpsd302v-b-20ji 200 44 pin pldcc industrial zpsd302v-b-20l 200 44 pin cldcc comm? zpsd302v-b-20m 200 44 pin pqfp comm? zpsd302v-b-20mi 200 44 pin pqfp industrial zpsd302v-b-20u 200 44 pin tqfp comm? zpsd302v-b-20ui 200 44 pin tqfp industrial zpsd302v-b-25j 250 44 pin pldcc comm? zpsd302v-b-25l 250 44 pin cldcc comm? zpsd302v-b-25m 250 44 pin pqfp comm? zpsd302v-b-25u 250 44 pin tqfp comm? zpsd303-b-70j 70 44 pin pldcc comm? zpsd303-b-70l 70 44 pin cldcc comm? zpsd303-b-70m 70 44 pin pqfp comm? zpsd303-b-70u 70 44 pin tqfp comm? zpsd303-b-90ji 90 44 pin pldcc industrial zpsd303-b-90li 90 44 pin cldcc industrial zpsd303-b-90mi 90 44 pin pqfp industrial zpsd303-b-90ui 90 44 pin tqfp industrial zpsd303-b-15j 150 44 pin pldcc comm? zpsd303-b-15l 150 44 pin cldcc comm? zpsd303-b-15m 150 44 pin pqfp comm? zpsd303-b-15u 150 44 pin tqfp comm? zpsd303r-b-70j 70 44 pin pldcc comm? zpsd303r-b-90ji 90 44 pin pldcc industrial zpsd303r-b-15j 150 44 pin pldcc comm? zpsd303v-b-20j 200 44 pin pldcc comm? zpsd303v-b-20ji 200 44 pin pldcc industrial zpsd303v-b-20l 200 44 pin cldcc comm? zpsd303v-b-20m 200 44 pin pqfp comm? zpsd303v-b-20mi 200 44 pin pqfp industrial zpsd303v-b-20u 200 44 pin tqfp comm? zpsd303v-b-20ui 200 44 pin tqfp industrial zpsd303v-b-25j 250 44 pin pldcc comm? zpsd303v-b-25l 250 44 pin cldcc comm? zpsd303v-b-25m 250 44 pin pqfp comm? zpsd303v-b-25u 250 44 pin tqfp comm? ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 78 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range zpsd311-b-70j 70 44 pin pldcc comm? zpsd311-b-70l 70 44 pin cldcc comm? zpsd311-b-70m 70 44 pin pqfp comm? zpsd311-b-70u 70 44 pin tqfp comm? zpsd311-b-90ji 90 44 pin pldcc industrial zpsd311-b-90li 90 44 pin cldcc industrial zpsd311-b-90mi 90 44 pin pqfp industrial zpsd311-b-90ui 90 44 pin tqfp industrial zpsd311-b-15j 150 44 pin pldcc comm? zpsd311-b-15l 150 44 pin cldcc comm? zpsd311-b-15m 150 44 pin pqfp comm? zpsd311-b-15u 150 44 pin tqfp comm? zpsd311r-b-70j 70 44 pin pldcc comm? zpsd311r-b-70m 70 44 pin pqfp comm? zpsd311r-b-90ji 90 44 pin pldcc industrial zpsd311r-b-90mi 90 44 pin pqfp industrial zpsd311r-b-15j 150 44 pin pldcc comm? zpsd311r-b-15m 150 44 pin pqfp comm? zpsd311v-b-15j 150 44 pin pldcc comm? zpsd311v-b-15l 150 44 pin cldcc comm? zpsd311v-b-15m 150 44 pin pqfp comm? zpsd311v-b-15u 150 44 pin tqfp comm? zpsd311v-b-20j 200 44 pin pldcc comm? zpsd311v-b-20ji 200 44 pin pldcc industrial zpsd311v-b-20l 200 44 pin cldcc comm? zpsd311v-b-20m 200 44 pin pqfp comm? zpsd311v-b-20mi 200 44 pin pqfp industrial zpsd311v-b-20u 200 44 pin tqfp comm? zpsd311v-b-20ui 200 44 pin tqfp industrial zpsd311v-b-25j 250 44 pin pldcc comm? zpsd311v-b-25l 250 44 pin cldcc comm? zpsd311v-b-25m 250 44 pin pqfp comm? zpsd311v-b-25u 250 44 pin tqfp comm? ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 79 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range zpsd312-b-70j 70 44 pin pldcc comm? zpsd312-b-70l 70 44 pin cldcc comm? zpsd312-b-70m 70 44 pin pqfp comm? zpsd312-b-70u 70 44 pin tqfp comm? zpsd312-b-90ji 90 44 pin pldcc industrial zpsd312-b-90li 90 44 pin cldcc industrial zpsd312-b-90mi 90 44 pin pqfp industrial zpsd312-b-90ui 90 44 pin tqfp industrial zpsd312-b-15j 150 44 pin pldcc comm? zpsd312-b-15l 150 44 pin cldcc comm? zpsd312-b-15m 150 44 pin pqfp comm? zpsd312-b-15u 150 44 pin tqfp comm? zpsd312r-b-70j 70 44 pin pldcc comm? zpsd312r-b-70m 70 44 pin pqfp comm? zpsd312r-b-90ji 90 44 pin pldcc industrial zpsd312r-b-90mi 90 44 pin pqfp industrial zpsd312r-b-15j 150 44 pin pldcc comm? zpsd312r-b-15m 150 44 pin pqfp comm? zpsd312v-b-20j 200 44 pin pldcc comm? zpsd312v-b-20ji 200 44 pin pldcc industrial zpsd312v-b-20l 200 44 pin cldcc comm? zpsd312v-b-20m 200 44 pin pqfp comm? zpsd312v-b-20mi 200 44 pin pqfp industrial zpsd312v-b-20u 200 44 pin tqfp comm? zpsd312v-b-20ui 200 44 pin tqfp industrial zpsd312v-b-25j 250 44 pin pldcc comm? zpsd312v-b-25l 250 44 pin cldcc comm? zpsd312v-b-25m 250 44 pin pqfp comm? zpsd312v-b-25u 250 44 pin tqfp comm? zpsd313-b-70j 70 44 pin pldcc comm? zpsd313-b-70l 70 44 pin cldcc comm? zpsd313-b-70m 70 44 pin pqfp comm? zpsd313-b-70u 70 44 pin tqfp comm? zpsd313-b-90ji 90 44 pin pldcc industrial zpsd313-b-90li 90 44 pin cldcc industrial zpsd313-b-90mi 90 44 pin pqfp industrial zpsd313-b-90ui 90 44 pin tqfp industrial zpsd313-b-15j 150 44 pin pldcc comm? zpsd313-b-15l 150 44 pin cldcc comm? zpsd313-b-15m 150 44 pin pqfp comm? zpsd313-b-15u 150 44 pin tqfp comm? ordering information obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx family 80 psd3xx ordering information (cont.) operating speed temperature part number (ns) package type range zpsd313r-b-70j 70 44 pin pldcc comm? zpsd313r-b-70m 70 44 pin pqfp comm? zpsd313r-b-90ji 90 44 pin pldcc industrial zpsd313r-b-90mi 90 44 pin pqfp industrial zpsd313r-b-15j 150 44 pin pldcc comm? zpsd313r-b-15m 150 44 pin pqfp comm? zpsd313v-b-20j 200 44 pin pldcc comm? zpsd313v-b-20ji 200 44 pin pldcc industrial zpsd313v-b-20l 200 44 pin cldcc comm? zpsd313v-b-20m 200 44 pin pqfp comm? zpsd313v-b-20mi 200 44 pin pqfp industrial zpsd313v-b-20u 200 44 pin tqfp comm? zpsd313v-b-20ui 200 44 pin tqfp industrial zpsd313v-b-25j 250 44 pin pldcc comm? zpsd313v-b-25l 250 44 pin cldcc comm? zpsd313v-b-25m 250 44 pin pqfp comm? zpsd313v-b-25u 250 44 pin tqfp comm? ordering information parts data sheet date affected changes may, 1995 psd3xx initial release may, 1998 zpsd3xx sram-less (r suffix) version added. pqfp package added. may, 1998 psd3xx pqfp package added, specifications updated, psd3xxl discontinued, some speed grades eliminated. february, 1999 psd3xxr, zpsd3xxr combined data sheets updated specifications 23. revisions history obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
psd3xx, zpsd3xx, zpsd3xxv, psd3xxr, zpsd3xxr, zpsd3xxrv 2/3 revision history table 1. document revision history date rev. description of revision may-1995 1.0 documents written in the wsi format. initial release may-1998 1.1 zpsd3xx sram-less (r suffix) version added. pqfp package added. psd3xx pqfp package added, specifications updated, psd3xxl discontinued, some speed grades eliminated. february, 1999 psd3xxr, zpsd3xxr combined data sheets updated specifications feb-1999 1.2 psd3xx zpsd3xx zpsd3xxv, psd3xxr zpsd3xxr zpsd3xxrv combined data sheets updated specifications 31-jan-2002 1.3 psd3xx, zpsd3xx, zpsd3xxv, psd3xxr, zpsd3xxr, zpsd3xxrv: low cost field programmable microcontroller peripherals front page, and back two pages, in st format, added to the pdf file any references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
3/3 psd3xx, zpsd3xx, zpsd3xxv, psd3xxr, zpsd3xxr, zpsd3xxrv information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)

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